patents tft lcd globally price

[1] The present invention relates to a cutting method of a large size TFT-LCD panel and a liquid crystal display unit to enhance a simplicity of process facility and a speediness through solving a problem of an increase of facilities due to manufacturing TFT-LCD panels of respective sizes and reducing a subsequently increased cost by enabling a mass production of a various size of TFT-LCD panels in one manufacturing line through using a TFT-LCD panel cut in a desired size that is manufactured in large size. Background Art

[5] Most of all as an outline, one pixel (composed of R. G. B. three sub-pixels) in the thin film transistor (TFT) - LCD is approximately as fine as 0.3 mm wide.

[6] Of course, the TFT included in the pixel is smaller than the pixel. Moreover, in order to meet a resolution of 1600x1200, 1,920,000 pixels are required and 5,760,000 TFTs are necessary if the sub-pixels are considered. Therefore, an overall process is very precise and demands a level of semiconductor process.

TFT process, a color filter (CF) process, a cell process and a module process. The cell process makes one panel with two glasses undergone the TFT process and the CF process. Then, the module process completes the manufacturing process by mounting the one TFT-LCD panel undergone the cell process in a real monitor or TV.

[8] First, the TFT process is the most basic core process for forming the most basic electrodes that provides an electrode for each cell. The process includes five process steps in order of forming a gate electrode, an insulating film, a semiconductor film, a data electrode, a protective film, and a pixel electrode that requires one or more pattern processes for each process step. Not only this pattern process that may be called a core

process in the processes of manufacturing the TFT-LCD panel is necessary in the TFT process but also a similar pattern process is necessary in the CF process.

TFT-LCD panel formed as hereinabove, the TFT-LCD panel is completed by providing a polarized plate on a surface of the TFT substrate and the CF substrate.

[11] The TFT-LCD panel of size demanded by a user may be produced in a large amount but the other TFT-LCD panel of less demand may be produced in only a limited amount since various sizes of the TFT-LCD panels completed as hereinabove require a difference in production line and in each process of the production line dependent on the sizes of the TFT-LCD panels. Disclosure of Invention Technical Problem

[13] The cutting method of a large size TFT-LCD panel of the present invention, provided to solve the hereinabove problems, has an object of enhancing a simplicity of process facility and speediness through solving a problem of an increase of facilities due to manufacturing TFT-LCD panels of different sizes and reducing a subsequently increased cost by enabling a mass production of a various size of TFT-LCD panels in one manufacturing line through using a TFT-LCD panel cut in a desired size that is manufactured in large size.

[14] The cutting method of a large size TFT-LCD panel formed as hereinabove can devise a simplicity in process and a profitability through solving a spatial enlargement and other costs increase due to an increase of facilities by equipping a facility"s process dependent on a size according to a production of TFT-LCD panels in various sizes, having an advantage of possibly producing a various size of the TFT-LCD panel asked by a user purpose or a user taste in a simple and convenient way, and solving an abandonment and reduction of the facilities due to a change in consumption dependent

[18] FIG. 4 illustrates a state of a scribe line set into a mid-depth of a color filter substrate and a thin film transistor substrate by diamond wheel in the cutting method of a large size TFT-LCD panel of the present invention.

[20] FIG. 6 illustrates a state completed after processing sealing a cut portion in the cutting method of a large size TFT-LCD panel of the present invention.

[27] In a completed large size TFT-LCD panel formed in a sequentially coupled configuration of a polarized plate, a color filter (CF) substrate, a liquid crystal layer, a thin film transistor (TFT) substrate and a polarized plate below the TFT substrate, a polarized plate stripping step that removes a portion of a predetermined width to be cut from the each polarized plate provided on a surface and an opposite surface of the large size TFT-LCD panel, a cutting location setting step that sets a portion not damaging a gate line and a data line of the TFT substrate through investigating a portion stripped in the polarized plate stripping step by microscope, a scribe line setting step that sets a first scribe line cutting the CF substrate into its mid-depth along the portion set in the cutting location setting step using a diamond wheel, a turning

over step that turns over the large size TFT-LCD panel to a side opposite from a side where a portion of the first scribe line is set after chucking one end of the large size TFT-LCD panel, a scribe line setting step that sets a second scribe line cutting the TFT substrate into its mid-depth in the stripped polarized plate portion along the portion set in the cutting location setting step which precisely corresponds with the set first scribe line using a diamond wheel after turning over the large size TFT-LCD panel, a tempering step that tempers for 30 minutes to form a natural crack in the scribe lines formed on the CF substrate and the TFT substrate of the large size TFT-LCD panel, a cutting step that cuts the CF substrate and the TFT substrate naturally cracked after the 30 minutes tempering step, and a sealing process step that sealing a cut portion formed in the cutting step, and

[28] In a completed large size TFT-LCD panel formed in a sequentially coupled configuration of a polarized plate, a color filter (CF) substrate, a liquid crystal layer, a thin film transistor (TFT) substrate and a polarized plate, a cutting location setting step that sets a portion to be cut, a scribe line setting step that sets a first scribe line cutting the CF substrate into its mid-depth along the portion set in the cutting location setting step using a diamond wheel, a turning over step that turns over the large size TFT-LCD panel to a side opposite from a side where a portion of the first scribe line is set after chucking one end of the large size TFT-LCD panel, a scribe line setting step that sets a second scribe line cutting the TFT substrate into its mid-depth along the portion set in the cutting line setting step which precisely corresponds with the set first scribe line, using a diamond wheel after turning over the large size TFT-LCD panel, a tempering step that tempers for 30 minutes to form a natural crack in the scribe lines formed on the CF substrate and the TFT substrate of the large size TFT-LCD panel, a cutting step that cuts the CF substrate and the TFT substrate naturally cracked after the 30 minutes tempering step, and a sealing process step that sealing a cut portion formed in the cutting step may accomplish the present invention object.

[29] Further, the present invention comprises a scribe line setting step that sets scribe lines simultaneously cutting the CF substrate and the TFT substrate into their mid-depths along the portions set in the cutting location setting step using a diamond wheel.

[30] The cutting method of a large size TFT-LCD panel further comprises a blocking off a light illuminated from a backlight through attaching a light blocking tape along a cut portion selected between the CF substrate and the TFT substrate or the both substrates or between the polarized plates located above the CF substrate and below the TFT substrate or the both polarized plates.

LCD panel 100 is formed in structure sequentially coupled of, a polarized plate 10, a color filter (CF) substrate 11, a liquid crystal layer 12, a thin film transistor (TFT) substrate 13 and a polarized plate 14.

[36] In order to cut the large size TFT-LCD panel 100 completed as hereinabove, a polarized plate stripping step is initially performed that removes a portion of a predetermined width to be cut from the each polarized plate 10 provided on a surface above the CF substrate 11 and an opposite surface below the TFT substrate 13.

[38] The TFT substrate 13 is exposed if the polarized plates 10 and 14 around the cutting portion are removed by its lengthwise direction. Since gate lines transferring a scanning signal and data line transferring a screen image signal are configured by innumerably crossing with each other and difficult to perceive by naked eyes, a cutting location setting step sets a portion not damaging the gate line and the data line of the TFT substrate through investigating a portion stripped on the polarized plate stripping step by microscope.

[43] To process a side opposite from a side where a portion of the first scribe line is set, the present step turns over the large size TFT-LCD panel 100 after chucking one end of the large size TFT-LCD panel 100.

[45] The present step sets a 2nd scribe line setting step cutting the TFT substrate 13 into its mid-depth in the portion of the stripped polarized plate 14 bonded with the TFT substrate 13 below along the portion set in the cutting location setting step which

precisely corresponds with the set first scribe line, using a diamond wheel after turning over the large size TFT-LCD panel 100. This step is also difficult and requires a skill of high precision to correspond with the set first scribe line.

[48] A natural crack is made if tempered for 30 minutes to form a natural crack in the scribe lines formed on the CF substrate 11 and the TFT substrate 13 of the large size TFT-LCD panel 100. Then, the air flows into a liquid crystal layer 12. If there is the air flow into the liquid crystal layer 12, the liquid crystal layer 12 is temporarily restricted from flowing out by the flowed in air.

[50] After the 30 minutes tempering step, the CF substrate 11 and the TFT substrate 13 are naturally cracked along the first scribe line and the second scribe line and the present step externally applies a certain amount of force in order to cut the large size TFT-LCD panel 100 along the scribe lines.

[52] The present step is the last step that applies a sealant 30 on a cut portion in the large size TFT-LCD panel 100 and the present invention is completed by applying the sealant 30.

[53] Through undergoing the process hereinabove, the large size TFT-LCD panel 100 is possible to be cut into a plural or multiple numbers without a many numbers of equipment and to meet a desired size of a demander or an operator.

[56] That is, in a large size TFT-LCD panel 100 completed of forming sequentially coupled, a polarized plate 10, a color filter (CF) substrate 11, a liquid crystal layer 12, a thin film transistor (TFT) substrate 13 and a polarized plate 14 below the TFT substrate 13, a cutting location setting step that sets a portion to be cut, a scribe line setting step that sets a first scribe line cutting the CF substrate 11 into its mid-depth along the portion set in the cutting location setting step using a diamond wheel, a turning over step that turns over the large size TFT-LCD panel 100 to a side opposite from a side where a portion of the first scribe line is set after chucking one end of the large size TFT-LCD panel 100, a scribe line setting step that sets a second scribe line cutting the TFT substrate 13 into its mid-depth along the portion set in the cutting location setting step corresponds with the set first scribe line, using a diamond wheel after turning over the large size TFT-LCD panel 100, a tempering step that tempers for

30 minutes to form a natural crack in the scribe lines formed on the CF substrate 11 and the TFT substrate 13 of the large size TFT-LCD panel 100, a cutting step that cuts the CF substrate 11 and the TFT 13 substrate naturally cracked after the 30 minutes tempering step, and a sealing process step that sealing a cut portion formed in the cutting step may configure the present invention.

[59] For example, after undergoing the sequentially processed cutting location setting steps of the first or the second exemplary embodiments through the polarized plate stripping step that removes a corresponding portion of a predetermined width to be cut from the polarized plates 10 and 14 provided on a surface of the CF substrate 11 and an opposite surface of the TFT substrate 13 like the first exemplary embodiment or without the polarized plate stripping step like the second exemplary embodiment, a scribe line setting step sets scribe lines simultaneously cutting the CF substrate 11 and the TFT substrate 13 into their mid-depths along the portion set in the cutting location setting step using a diamond wheel.

TFT substrate 13 by applying the same scribe line depth and the like enables not only an abridgement of the operation process but also a precise setting job.

[61] The present exemplary embodiment may or may not include the polarized plate stripping step like the first or second exemplary embodiment, and the subsequent steps may proceed in the same sequence as tempering step for the natural crack, cutting step cutting the CF substrate 11 and the TFT substrate 13 and sealing process step .

[62] Meanwhile, when a light from the backlight unit through the TFT-LCD panel 100 processed by the respective exemplary embodiments is illuminated to display a corresponding image, the image may be displayed with an image quality relatively unclear at a portion corresponding to the cutting portion.

[64] Here, the light blocking tape 20 may be attached in a range covering any cut portions of the CF substrate 11 and the TFT substrate 13 or the both substrates 11 and 13 as shown in FIG. 7.

10 bonded above with the CF substrate 11 or at a periphery of the polarized plate 14 bonded below with the TFT substrate 14 which are removed with the set cutting portion, may maximize a clearness of the screen quality when the light from the back light unit is illuminated on the cut portion of the TFT-LCD panel 100 completed by cutting into a desirable size.

[67] Meanwhile, as shown in FIG. 9 of other exemplary embodiment, a transparent tape is used to cover an outer peripheral edge of the CF substrate 11 and the TFT substrate 13 after sealing the outer peripheral edge with an ultraviolet sealant 31 while the CF substrate 11 and the TFT substrate 13 are in bonded state.

[68] Further, though not shown in the drawings, the peripheries of the CF substrate 11 and the TFT substrate 13 may be covered by tape-processing or may be fixed by clipping and the like.

[70] Further, FIG. 10 and FIG. 11 illustrate an application of the TFT-LCD panel according to the cutting method provided by the present invention. FIG. 10 is a brief exploded perspective view of a liquid crystal display unit. FIG. 11 is a brief cross sectional view of FIG. 10.

[71] As shown in FIG. 10 and FIG. 11, the cut processed TFT-LCD panel 100 equipped with the backlight unit (not shown in drawing) below undergoes a series of course coupling a top sash 2 corresponding to an upper frame with an accommodating frame 3 accommodating the TFT-LCD panel 100 and the backlight unit to be used for the liquid crystal display unit.

[72] Here, when the TFT-LCD panel 100 cut processed in a desired size according to the present invention is received in the top sash 2 and the accommodating frame 3, a realization of a clear screen may be difficult since a slight difference may be produced, not accurately fixing the TFT-LCD panel 100, and producing a flowing phenomena because of the internal difference.

[74] Accordingly, in order to prevent the flowing phenomena, that is the flowing phenomena of the received TFT-LCD panel 100, attaching a plurality of both-faces tape 4 at the outer peripheral edge on the top sash 2 surface and attaching a plurality of both-faces tape 4 at the outer peripheral edge on the accommodating frame 3 surface as well is preferable to completely prevent the flowing phenomena.

[76] Therefore, since a large size TFT-LCD panel may be miniaturized for an application to various video games, monitors or cell phone liquid crystal displays through cut processing the large size TFT-LCD panel without a separate manufacturing line for manufacturing process according to present invention, an industrial applicability expecting an effective reduction of manufacturing facility and its value may be recognized.

FIG. 1 is a schematic view of one pixel unit in the TFT-LCD array substrate according to the first embodiment of the present invention. FIG. 2 is a partial cross-sectional view of the TFT along the line 1b-1b in FIG. FIG. 3 is a partial cross-sectional view of the gate line along line 2b-2b of FIG.

As shown in FIGS. 1, 2, and 3, the TFT-LCD array substrate according to the first embodiment of the present invention includes a substrate (for example, a transparent substrate) 21, a gate line 22a formed on the substrate 21, and a gate line 22a. The gate electrode 22b to be connected (or branched therefrom), the first insulating layer 23 formed in the gate line 22a and the gate electrode 22b, the semiconductor layer 24, and the source / drain region of the semiconductor 24 to expose the channel. The formed ohmic contact layer 25, the gate line 22a and the gate electrode 22b, the first insulating layer 23, and the second gate insulating layer formed on the substrate 21 so as to cover the side walls of the semiconductor layer 24 and the ohmic contact layer 25. 26, and a source electrode via hole 27c and a drain electrode via hole formed above the ohmic contact layer of the source region and the drain region, respectively. 27 d, formed in the second insulating layer 26, formed in the second insulating layer 26, the data line 32 contacting the ohmic contact layer 25 in the source region via the source electrode via hole 27 c and the source electrode 27 a connected thereto. The drain electrode 27b that is in contact with the ohmic contact layer 25 in the drain region through the drain electrode via hole 27d, the passivation layer 28 formed on the data line 32, the source electrode 27a, and the drain electrode 27b, and the second insulating layer 26 And a pixel electrode 31 connected to the drain electrode 27b. Here, the gate line 22a and the data line 32 intersect each other to define a pixel region.

FIGS. 4 to 9 show a manufacturing method for manufacturing the TFT-LCD array substrate according to the first embodiment of the present invention by employing four photolithography processes.

A photoresist layer (for example, a positive photoresist, not shown) is applied to the laminate obtained by the process shown in FIG. 4, and this photoresist layer is exposed with a gray-tone mask to form a photoresist layer. An unexposed region of the photoresist, a partially exposed region of the photoresist (ie, a gray tone region), and a photoresist fully exposed region are obtained. The exposed photoresist layer is developed to obtain a gray tone photoresist pattern (not shown). Here, the photoresist layer in the unexposed region of the photoresist is completely left, and a complete photoresist remaining region corresponding to a portion where the gate line and the gate electrode are to be formed on the array substrate is obtained. The photoresist layer in the photoresist partial exposure region is partially left, and a photoresist partial residual region corresponding to a portion where a TFT channel is to be formed on the array substrate is obtained. The photoresist layer in the completely exposed region of the photoresist is completely removed, resulting in a region without photoresist.

複数ステップのドライエッチングが終わった後、フォトレジストのアッシング工程を行い、フォトレジスト部分的残留領域のフォトレジスト層を除去する。アッシングガスとしては、ＳＦ６、Ｏ２又はＳＦ６／Ｏ２混合ガス等を選択すれば良い。これと同時に、フォトレジスト完全残留領域のフォトレジスト層も部分的に除去されるため、厚さが薄くなる。アッシングが終わった後、図６に示すように、フォトレジスト部分的残留領域におけるフォトレジスト層も除去されることによって、形成しようとするＴＦＴチャンネル中のオーミック接触層２５が露出される。そして、下の半導体層２４を露出させるように、ドライエッチング工程によって露出されたオーミック接触層２５をエッチングして除去し、ＴＦＴのチャンネル４０を形成する。エッチングガスとしては、ＳＦ６／Ｃｌ２、又はＳＦ６／ＨＣｌ等のガスを選択すれば良い。チャンネルにおけるオーミック接触層を完全にエッチング除去するために、一般にオーバーエッチング法を取る。After the multi-step dry etching is completed, a photoresist ashing process is performed to remove the photoresist layer in the photoresist partially remaining region. As the ashing gas, SF 6 , O 2, SF 6 / O 2 mixed gas, or the like may be selected. At the same time, the photoresist layer in the photoresist completely remaining region is also partially removed, so that the thickness is reduced. After the ashing is finished, the ohmic contact layer 25 in the TFT channel to be formed is exposed by removing the photoresist layer in the photoresist partially remaining region as shown in FIG. Then, the ohmic contact layer 25 exposed by the dry etching process is removed by etching so that the lower semiconductor layer 24 is exposed, and the TFT channel 40 is formed. As an etching gas, a gas such as SF 6 / Cl 2 or SF 6 / HCl may be selected. In order to completely etch away the ohmic contact layer in the channel, an over-etching method is generally used.

図７に示すように、ＴＦＴのチャンネルが形成された後、残りのフォトレジストパターンを除去し、ＰＥＣＶＤ法によって基板２１の露出面、オーミック接触層２５及び半導体層２４の露出部分に、厚さが約２５００Åである第２の絶縁層２６を堆積する。第２の絶縁層２６は酸化物、窒化物、又は酸窒化物を含んでも良い。ＰＥＣＶＤにおいて対応する反応ガスはＳｉＨ４、ＮＨ３又はＮ２、或いはＳｉＨ２Ｃｌ２、ＮＨ３又はＮ２であっても良い。第２の絶縁層２６はＴＦＴのチャンネルを直接覆うため、ＴＦＴのチャンネルを保護する作用がある。As shown in FIG. 7, after the TFT channel is formed, the remaining photoresist pattern is removed, and the exposed surface of the substrate 21, the ohmic contact layer 25, and the exposed portion of the semiconductor layer 24 have a thickness by PECVD. A second insulating layer 26, which is about 2500 mm, is deposited. The second insulating layer 26 may include oxide, nitride, or oxynitride. The corresponding reaction gas in PECVD may be SiH 4 , NH 3 or N 2 , or SiH 2 Cl 2 , NH 3 or N 2 . Since the second insulating layer 26 directly covers the TFT channel, the second insulating layer 26 has an effect of protecting the TFT channel.

As shown in FIG. 1, after the passivation layer 28 is etched and patterned, the photoresist in the passivation layer is retained, and a transparent pixel electrode material having a thickness of about 400 mm by sputtering or thermal evaporation on the obtained substrate Layer 29 is deposited (see FIGS. 2 and 3). This pixel electrode material layer may contain indium tin oxide (ITO), indium zinc oxide (IZO), or the like. The photoresist is peeled off with the chemical solution, and the transparent conductive material layer in the photoresist is also peeled off to form the pixel electrode 31 (see FIG. 2), thereby completing the manufacture of the TFT-LCD array substrate.

Global Thin Film Transistor (TFT) Display Market, By Technology (Plasma Display (PDP), Organic Light Emitting Diode (OLED), Other), Type (Twisted Nematic, In-Plane Switching, Advanced Fringe Field Switching, Multi-Domain Vertical Alignment, Advanced Super View, Cell Technology), Panel Type (A_MVA, ASV, MVA, S_PVA, P-IPS), End Use (Domestic Use, Industrial Use) – Industry Trends and Forecast to 2029

Global Thin Film Transistor (TFT) Display Market was valued at USD 270.26 million in 2021 and is expected to reach USD 968.64 million by 2029, registering a CAGR of 17.30% during the forecast period of 2022-2029. Twisted Nematic accounts for the largest type segment in the respective market owing to its low cost. The market report curated by the Data Bridge Market Research team includes in-depth expert analysis, import/export analysis, pricing analysis, production consumption analysis, and pestle analysis.

A thin-film-transistor display refers to a form of LCD that uses TFT technology for enhancing image quality including addressability and contrast. These displays are commonly utilized in mobile phones, handheld video game systems, projectors, computer monitors, television screens, navigation systems and personal digital assistants.

The increase in the smartphone and tablet proliferation acts as one of the major factors driving the growth of thin film transistor (TFT) display market. Technological advancements are leading a radical shift from traditional slow, bulky and imprecise resistive mono touch to highly sensitive multi-touch capacitive screen have a positive impact on the industry.

The increase in application areas of large e thin film transistor (TFT) display due to the advantages offered by these paper displays in terms of user experience, manufacturing cost, readability, and energy consumption further influence the market.

Additionally, rapid urbanization, change in lifestyle, surge in investments and increased consumer spending positively impact the thin film transistor (TFT) display market.

On the other hand, high cost associated with the manufacturing is expected to obstruct market growth. Also, lack of awareness and low refresh rate are projected to challenge the thin film transistor (TFT) display market in the forecast period of 2022-2029.

This thin film transistor (TFT) display market report provides details of new recent developments, trade regulations, import-export analysis, production analysis, value chain optimization, market share, impact of domestic and localized market players, analyses opportunities in terms of emerging revenue pockets, changes in market regulations, strategic market growth analysis, market size, category market growths, application niches and dominance, product approvals, product launches, geographic expansions, technological innovations in the market. To gain more info on thin film transistor (TFT) display market contact Data Bridge Market Research for an Analyst Brief, our team will help you take an informed market decision to achieve market growth.

The COVID-19 has impacted thin film transistor (TFT) display market. The limited investment costs and lack of employees hampered sales and production of electronic paper (e-paper) display technology. However, government and market key players adopted new safety measures for developing the practices. The advancements in the technology escalated the sales rate of the thin film transistor (TFT) display as it targeted the right audience. The increase in sales of devices such as smart phones and tablets across the globe is expected to further drive the market growth in the post-pandemic scenario.

The thin film transistor (TFT) display market is segmented on the basis of technology, type, panel type and end-use. The growth amongst these segments will help you analyze meager growth segments in the industries and provide the users with a valuable market overview and market insights to help them make strategic decisions for identifying core market applications.

The thin film transistor (TFT) display market is analysed and market size insights and trends are provided by country, technology, type, panel type and end-use as referenced above.

The countries covered in the thin film transistor (TFT) display market report are U.S., Canada, Mexico, Brazil, Argentina, Rest of South America, Germany, Italy, U.K., France, Spain, Netherlands, Belgium, Switzerland, Turkey, Russia, Rest of Europe, Japan, China, India, South Korea, Australia, Singapore, Malaysia, Thailand, Indonesia, Philippines, Rest of Asia-Pacific, Saudi Arabia, U.A.E, South Africa, Egypt, Israel, Rest of Middle East and Africa (MEA).

North America dominates the thin film transistor (TFT) display market because of the introduction of advanced technology along with rising disposable income of the people within the region.

The thin film transistor (TFT) display market competitive landscape provides details by competitor. Details included are company overview, company financials, revenue generated, market potential, investment in research and development, new market initiatives, global presence, production sites and facilities, production capacities, company strengths and weaknesses, product launch, product width and breadth, application dominance. The above data points provided are only related to the companies" focus related to thin film transistor (TFT) display market.

As a Zhongguancun enterprise, BOE has always adhered to technology-driven innovation. According to statistics, BOE"s 2018 shipments of LCD TV panels exceeded that of,LG Display Co, one of the world"s biggest manufacturers of display panels used in smartphones and televisions, ranking first in the world that year.

"The display shipments of BOE increased by 24 percent year-on-year in 2018, and its dispatch area increased by 45 percent year-on-year, which is the highest growth among the top five panel makers in the world," According to Sigmaintell Consulting analysts, who added that BOE achieved remarkable results in 2018: the world"s first 10.5 generation TFT-LCD mass production line was put into operation, and its TV panel production capacity increased by over 40 percent.

Global shipments of LCD TV panels in the first quarter of 2018 [Photo provided to chinadaily.com.cn]BOE accelerated its technology upgrading and achieved a new breakthrough in liquid crystal display technology in 2018. By applying megapixel partitioning technology, BOE 4K display achieved a 100,000-level ultra-high dynamic contrast ratio, with a color depth up to 12bits, so that the LCD display perfectly shows the ultra high definition display effect.

Recently, the US patent service agency IFI Claims released the 2018 US statistics report on patent authorization. BOE"s global ranking had jumped to 17th, with patents granted in America reaching 1,634, an increase of 16 percent. BOE is now the fastest-growing company among the TOP 20 enterprises listed by IFI Claims.

In 2018, BOE added 9,958 new patent applications, 90 percent of them invention patents and 38 percent overseas patents covering the United States, Europe, Japan, South Korea and other countries and regions. The total number of patents held by the company exceeds 70,000.

Over a decade ago, due to the lack of core technologies in the field of semiconductor displays, China"s electronic information industry was shrouded in the shadow of the "lack of LCD screens", and was even unable to independently manufacture a complete LCD TV.

Acquisition of Hyundai Electronics" LCD panel businesses gave Chinese semiconductor companies a chance to break through technological limitations. [Photo provided to chinadaily.com.cn]A group of semiconductor companies like BOE seized the opportunity to acquire Hyundai Electronics" LCD panel businesses. After digesting, absorbing and re-innovating, the companies mastered liquid crystal display technology and ended the dependence on imports in the Chinese semiconductor and display industries.

of a technology market is not synchronous to technology [10] Pénin, J., “Strategic uses of patents in markets for technology: A story

takes into account information on patents granted by the U.S. directly observed patent value - An empirical analysis of Ocean Tomo

obtained for patents granted by non-U.S. organizations, this for exploiting patented technological knowledge assets in the markets

related technologies and applications using the same analysis of global patents and trademarks,” Technological Forecasting

A thin-film-transistor liquid-crystal display (TFT LCD) is a variant of a liquid-crystal display that uses thin-film-transistor technologyactive matrix LCD, in contrast to passive matrix LCDs or simple, direct-driven (i.e. with segments directly connected to electronics outside the LCD) LCDs with a few segments.

In February 1957, John Wallmark of RCA filed a patent for a thin film MOSFET. Paul K. Weimer, also of RCA implemented Wallmark"s ideas and developed the thin-film transistor (TFT) in 1962, a type of MOSFET distinct from the standard bulk MOSFET. It was made with thin films of cadmium selenide and cadmium sulfide. The idea of a TFT-based liquid-crystal display (LCD) was conceived by Bernard Lechner of RCA Laboratories in 1968. In 1971, Lechner, F. J. Marlowe, E. O. Nester and J. Tults demonstrated a 2-by-18 matrix display driven by a hybrid circuit using the dynamic scattering mode of LCDs.T. Peter Brody, J. A. Asars and G. D. Dixon at Westinghouse Research Laboratories developed a CdSe (cadmium selenide) TFT, which they used to demonstrate the first CdSe thin-film-transistor liquid-crystal display (TFT LCD).active-matrix liquid-crystal display (AM LCD) using CdSe TFTs in 1974, and then Brody coined the term "active matrix" in 1975.high-resolution and high-quality electronic visual display devices use TFT-based active matrix displays.

The circuit layout process of a TFT-LCD is very similar to that of semiconductor products. However, rather than fabricating the transistors from silicon, that is formed into a crystalline silicon wafer, they are made from a thin film of amorphous silicon that is deposited on a glass panel. The silicon layer for TFT-LCDs is typically deposited using the PECVD process.

Polycrystalline silicon is sometimes used in displays requiring higher TFT performance. Examples include small high-resolution displays such as those found in projectors or viewfinders. Amorphous silicon-based TFTs are by far the most common, due to their lower production cost, whereas polycrystalline silicon TFTs are more costly and much more difficult to produce.

The twisted nematic display is one of the oldest and frequently cheapest kind of LCD display technologies available. TN displays benefit from fast pixel response times and less smearing than other LCD display technology, but suffer from poor color reproduction and limited viewing angles, especially in the vertical direction. Colors will shift, potentially to the point of completely inverting, when viewed at an angle that is not perpendicular to the display. Modern, high end consumer products have developed methods to overcome the technology"s shortcomings, such as RTC (Response Time Compensation / Overdrive) technologies. Modern TN displays can look significantly better than older TN displays from decades earlier, but overall TN has inferior viewing angles and poor color in comparison to other technology.

The transmittance of a pixel of an LCD panel typically does not change linearly with the applied voltage,sRGB standard for computer monitors requires a specific nonlinear dependence of the amount of emitted light as a function of the RGB value.

Less expensive PVA panels often use dithering and FRC, whereas super-PVA (S-PVA) panels all use at least 8 bits per color component and do not use color simulation methods.BRAVIA LCD TVs offer 10-bit and xvYCC color support, for example, the Bravia X4500 series. S-PVA also offers fast response times using modern RTC technologies.

TFT dual-transistor pixel or cell technology is a reflective-display technology for use in very-low-power-consumption applications such as electronic shelf labels (ESL), digital watches, or metering. DTP involves adding a secondary transistor gate in the single TFT cell to maintain the display of a pixel during a period of 1s without loss of image or without degrading the TFT transistors over time. By slowing the refresh rate of the standard frequency from 60 Hz to 1 Hz, DTP claims to increase the power efficiency by multiple orders of magnitude.

Due to the very high cost of building TFT factories, there are few major OEM panel vendors for large display panels. The glass panel suppliers are as follows:

External consumer display devices like a TFT LCD feature one or more analog VGA, DVI, HDMI, or DisplayPort interface, with many featuring a selection of these interfaces. Inside external display devices there is a controller board that will convert the video signal using color mapping and image scaling usually employing the discrete cosine transform (DCT) in order to convert any video source like CVBS, VGA, DVI, HDMI, etc. into digital RGB at the native resolution of the display panel. In a laptop the graphics chip will directly produce a signal suitable for connection to the built-in TFT display. A control mechanism for the backlight is usually included on the same controller board.

The low level interface of STN, DSTN, or TFT display panels use either single ended TTL 5 V signal for older displays or TTL 3.3 V for slightly newer displays that transmits the pixel clock, horizontal sync, vertical sync, digital red, digital green, digital blue in parallel. Some models (for example the AT070TN92) also feature input/display enable, horizontal scan direction and vertical scan direction signals.

New and large (>15") TFT displays often use LVDS signaling that transmits the same contents as the parallel interface (Hsync, Vsync, RGB) but will put control and RGB bits into a number of serial transmission lines synchronized to a clock whose rate is equal to the pixel rate. LVDS transmits seven bits per clock per data line, with six bits being data and one bit used to signal if the other six bits need to be inverted in order to maintain DC balance. Low-cost TFT displays often have three data lines and therefore only directly support 18 bits per pixel. Upscale displays have four or five data lines to support 24 bits per pixel (truecolor) or 30 bits per pixel respectively. Panel manufacturers are slowly replacing LVDS with Internal DisplayPort and Embedded DisplayPort, which allow sixfold reduction of the number of differential pairs.

Kawamoto, H. (2012). "The Inventors of TFT Active-Matrix LCD Receive the 2011 IEEE Nishizawa Medal". Journal of Display Technology. 8 (1): 3–4. Bibcode:2012JDisT...8....3K. doi:10.1109/JDT.2011.2177740. ISSN 1551-319X.

K. H. Lee; H. Y. Kim; K. H. Park; S. J. Jang; I. C. Park & J. Y. Lee (June 2006). "A Novel Outdoor Readability of Portable TFT-LCD with AFFS Technology". SID Symposium Digest of Technical Papers. AIP. 37 (1): 1079–82. doi:10.1889/1.2433159. S2CID 129569963.

The publication will be available on the USPTO home page in the Searchable Patent Databases section http://www.uspto.gov/patft and information about the application will also be available on Private PAIR and Patent Center.Will assignee data be printed on a patent application publication?

When an application is published, the publication will be included on the USPTO home page in the Searchable Patent Databases section at http://www.uspto.gov/patft and information on the published application will be included in the publicly accessible portion of Patent Center athttps://patentcenter.uspto.gov.How can I ensure that the bibliographic information for a patent application is printed correctly?

No. Third parties do not having standing to demand that the Office issue or refuse to issue a certificate of correction. See Hallmark Card, Inc. v. Lehman, 959 F. Supp. 539, 543-44, 42 USPQ2d 1134, 1138 (D.D.C. 1997). The Office is, however, cognizant of the need for the public to have correct information about published patents and may therefore accept information about mistakes in patents from third parties and may issue certificates of correction based upon that information (whether or not it is accompanied by a specific request for issuance of a certificate of correction).Must the title of the invention appear as a heading on the first page of the specification?

If an applicant or a practitioner chooses not to print copies of U.S. patents and patent applications publications through the USPTO Patents on the Web system or through the E-Patent Reference system, commercial sources that provide patents very quickly and inexpensively are available, and copies of U.S. patents and patent application publications are also available at the Patent and Trademark Depository Libraries (PTDLs). A listing of PTDLs is located on the USPTO web site athttp://www.uspto.gov/web/offices/ac/ido/ptdl/ptdlib_1.html . Additionally, the cost of patents if ordered from the USPTO Office of Public Records is very reasonable ($3). For more information, see "USPTO to Provide Electronic Access to Cited U.S. Patent References with Office Actions and Cease Supplying Paper Copies," 1282 OG 109 (May 18, 2004).http://www.uspto.gov/web/offices/com/sol/og/2004/week20/pataces.htm .How would the Office treat non-compliant amendments filed in response to an Ex Parte Quayle action?

On January 5, 2002, a foreign counsel in Germany receives a communication from the European Patent Office that includes a list of citations of patents. On January 8, the foreign counsel, pursuant to the standing instructions of US counsel, sends by overnight mail, a copy of the communication from the EPO. The document is received by US counsel on January 12, 2002. On January 30, the US counsel reviews the document and discovers a previously uncited patent. A copy of the patent and an IDS is then prepared and filed by the US counsel on February 11, 2002.

On January 5, 2002, the French counsel receives a search report from the European Patent Office that includes a list of six patents. On January 20, 2002, the US counsel receives from French counsel (by overnight mail) a copy of the communication from the EPO and suggests that the US counsel review the search report and "take appropriate action." On January 25, 2002, the French counsel provides a copy of the search report to the applicant. On January 30, 2002, the US counsel reviews the document and discovers a previously uncited patent. A copy of the patent and an IDS is then prepared and filed by the US counsel on February 14, 2002.

An applicant based in Chicago, Illinois, hires US counsel to prepare an application suitable for filing in the United States and the European Patent Office. The US counsel engages a German attorney to assist in the review and editing of the application to take account of issues relevant to EPO practice. The US counsel then reviews the edited application, approves the changes, and files it in the United States. The US counsel then directs the German attorney to file the application in the EPO. During prosecution of the US case, the US counsel receives an office action citing three patents.

On December 1, 2001, the US counsel sends the three patents to the German attorney for review and appropriate action. On January 5, 2002, the German attorney receives a search report from the EPO that cites the three previously cited patents, plus a fourth patent, designating all as "X" references. On January 15, the German attorney reviews the fourth patent and compares it to the three patents cited in the US prosecution. The German attorney concludes that the fourth patent is duplicative of one of the three patents, and takes no further action.

On March 1, 2002, during a routine status inquiry, the US counsel is informed of the citation of the fourth patent by the EPO and the decision of the German attorney that the information in the newly cited patent was duplicative of the three patents previously cited by the USPTO. The US counsel also obtains copies of the newly cited patent on this date. On March 5, 2002, the US counsel files an IDS containing the newly cited patent.

In this example, the USPTO would consider the participation of the German counsel in the prosecution and decision-making as to the relevance of the newly cited art vis- -vis the previously cited three patents to be a material participation in the US prosecution. As such, the German counsel would be considered by the USPTO to be a party covered by 37 CFR 1.56(c), and as such, would evaluate compliance with 37 CFR 1.704(d) from the date that the foreign counsel first learned of the fourth patent (i.e., the newly cited reference).I have some questions regarding patent term adjustment (PTA). Who can help me?

The United States Patent and Trademark Office does not print the expiration date on issued patents because the actual date a patent will expire is dependent upon a number of future events. The actual date any particular patent will expire is, for example, dependent upon whether: (1) all maintenance fees are timely paid; (2) the patent is disclaimed, either by a statutory disclaimer of all claims or a terminal disclaimer; (3) all of the claims of the patent are canceled during a reexamination proceeding; or (4) an extension under 35 U.S.C. 156 is granted. Since less than forty percent of patentees pay all three maintenance fees, an expiration date based upon a calculation of date that is twenty years from the earliest filing date under 35 U.S.C. 111(a), 120, 121, 363, or 365(c) plus any calculated extension under 35 U.S.C. 154(b) would be incorrect and misleading over sixty percent of the time. However, the front page of the patent will indicate the number of days of term adjustment to which the patent is entitled.May an applicant obtain patent term adjustment even if prosecution is less than 3 years?

No, they are published with a notice in the Official Gazette - Patents, stating that the application has been filed. Reissue applications are open to public inspection. See 37 CFR 1.11(b). If you receive a filing receipt for a reissue application and the filing receipt has a projected publication date, contact the Customer Service Representative where your application is assigned. They can have the application withdrawn from publication under 35 U.S.C. 122(b).When does the applicant have to pay the publication fee?

Section 1.99 provides that a submission by a member of the public of patents or publications relevant to a pending published application will be entered in the application file if the submission complies with the requirements of § 1.99 and the application is still pending when the submission and application file are brought before the examiner. Section 1.99(d) provides that a submission under § 1.99 may not include any explanation of the references, or any other information. The Office will dispose of any explanation or information if included in a submission under § 1.99. To ensure that there is no protest, the Office will review submissions under § 1.99 to determine whether they are limited to patents and publications before the submission is placed in the file of the application and forwarded to the examiner. The submission under § 1.99 will not be placed in the file of the application, if the explanation of the references and any other information included in the submission are integrated in the references and cannot be extracted easily, or if the references are highlighted.If an applicant wants to publish an amended version of the application when he or she files a CPA, when must the applicant file the EFS version of the amended application for the publication?

A petition to abandon an application to avoid publication under 37 CFR 1.138(c) and the fee (currently $130) set forth in 37 CFR 1.17(h) may be filed if there is sufficient time (i.e., more than 4 weeks) to permit the appropriate officials to recognize the abandonment and remove the application from the publication process, i.e., the petition must be received by the Office of Patent Publication no later than four weeks before the projected publication date. The petition will not be granted unless the petition and the fee are received more than four weeks prior to the projected date of publication (found on the filing receipt). The petition and the fee (or an authorization to charge the fee to a deposit account) should be mailed to Mail Stop Express Abandonment Commissioner for Patents, P.O. Box 1450 Alexandria, VA 22313-1450, or faxed to the Office of Patent Publication, PGPub Division, at (703) 305-8568.I received a filing receipt in a Continued Prosecution Application (CPA), but the filing receipt has nothing specific to the CPA, except an indication of a projected publication date. Why doesn"t the filing receipt indicate that it is for a CPA rather tha

Mail Stop PGPUB, Commissioner for Patents, P.O. Box 1450 Alexandria, VA 22313-1450.How do I request an early publication after I have submitted my application?

The CREATE Act was enacted on December 10, 2004, and is effective for all patents, including reissued patents, granted on or after the enactment date. In other words, it is effective for all patent applications pending on or after December 10, 2004. The CREATE Act also effectively makes the 1999 amendment to 35 U.S.C. 103(c) applicable to any applications filed prior to November 29, 1999 and were pending on December 10, 2004. The 1999 amendment to 35 U.S.C. 103(c) added certain commonly owned or assigned prior art under 35 U.S.C. 102(e) to the prior art under 35 U.S.C. 102(f) and (g) that can be disqualified under 35 U.S.C. 103(c). For the 1999 amendment, see § 4807 of the American Inventors Protection Act of 1999 ( see Pub. L. 106-113, 113 Stat. 1501, 1501A-591 (1999)).

Because the CREATE Act applies only to patents granted on or after December 10, 2004, the recapture doctrine may prevent the presentation of claims in reissue applications that had been amended or cancelled (e.g., to avoid a rejection under 35 U.S.C. 103(a) based upon subject matter that may now be disqualified under the CREATE Act) during the prosecution of the application which resulted in the patent being issued. See H.R. Rep. No. 108-425, at 6-7 (2003). The CREATE Act also applies to all reexamination proceedings in which the patent being reexamined was granted on or after December 10, 2004.What applications qualify for the prior art exclusion of 35 U.S.C. 103(c), as amended by the AIPA, of commonly owned or assigned prior art?

The revisions to 35 U.S.C. 102(e) and 374 in Pub. L. 107-273 completely replaced the corresponding AIPA versions and are retroactively effective to the effective date of the AIPA amendments to 35 U.S.C. 102(e) and 374 (November 29, 2000). The following briefly summarizes the major differences: Revised 35 U.S.C. 102(e) (Pub. L. 107-273) generally accords the same prior art date to references of the same application whether it was published as a US patent, a US patent application publication or a WIPO publication. There are limited situations where the US patent may have a different prior art date under 35 U.S.C. 102(e) than the corresponding US patent application publication or a WIPO publication. For example, when the application is based directly on the national stage (35 U.S.C. 371) of an International Application (IA) filed prior to November 29, 2000, however, the US patent has a different 35 U.S.C. 102(e) date for prior art purposes (the 35 U.S.C. 371 date) than the US application publication or the WIPO publication (no 102(e) date). Under the AIPA (prior to the Technical Amendments Act), a US patent application publication of an application could have a much earlier 35 U.S.C. 102(e) date than the corresponding US patent of that same application. This resulted from that fact that the prior art date under 35 U.S.C. 102(e) for US patent application publications could be the international filing dates (even prior to 11/29/00) if certain conditions were met, but US patents could never be prior art under 35 U.S.C. 102(e) as of the international filing date.

Revised 35 U.S.C. 102(e) and 374 in Pub. L. 107-273 are applicable to all applications under examination, no matter when filed and all US patents under reexamination or being contested. 35 U.S.C. 102(e) and 374 per the AIPA (prior to the Technical Amendments Act) were only applicable to certain applications, e.g., those filed on or after November 29, 2000 or voluntarily published under 35 U.S.C. 122(b).

Yes, see Guidelines Concerning the Implementation of Changes to 35 USC 102(g) and 103(c) and the Interpretation of the Term "Original Application" in the American Inventors Protection Act of 1999, Notice, 1233 OG 54 (April 11, 2000).When did the 35 U.S.C. 102(e) dates stop being printed on patents?

The Office stopped printing the 102(e) dates on patents with the issue of May 28, 2002.Are the 35 U.S.C. 102(e) dates printed on patents issued before May 28, 2002 accurate in view of the amended 35 U.S.C. 102(e)?

In most situations, the 35 U.S.C. 102(e) dates printed on patents are accurate ( e.g. , a patent issued from the national stage of an international application filed before 11/29/00). In a few situations, the printed 35 U.S.C. 102(e) dates may not be accurate because the 35 U.S.C. 102(e) dates printed on patents are based on the entry date of the national stage and not the international filing date (e.g., a patent issued from the national stage of an international application filed on or after 11/29/00). A US patent issued from an international application filed on or after 11/29/00 may have a 35 U.S.C. 102(e) date as of the international filing date or none under the amended 35 U.S.C. 102(e). See Flowchart I [PDF] .Will the 35 U.S.C. 102(e) dates be printed on patents in the future?

Yes. 35 U.S.C. 102(e), as amended by the Technical Amendments Act, must be applied toall patent applications no matter when filed . In other words, the revised statute applies to patent applications filed prior to the effective date of November 29, 2000 as well as to patent applications filed on or after November 29, 2000. Additionally, the revised 35 U.S.C. 102(e) applies to all patents under reexamination or other proceedings challenging the patent. One of the reasons for the Technical Amendments Act was to provide for application of the revised statute to all patent applications, regardless of the filing date, and all patents.What is meant by the "National Stage" of an international application (IA)?

A register of attorneys and agents entitled to represent applicants for patents is maintained by the U.S. Patent and Trademark Office (USPTO). General Requirements for Admission to the Examination for Registration to Practice in Patent Cases Before the U.S. Patent and Trademark Office booklet describes the requirements for registration as an attorney or agent. It includes the application for registration to practice before the USPTO, requirements for admission to the examination, a description of the exam content, the deadline for filing, and a list of the cities where the exam is given. You may visit the USPTO"s Office of Enrollment and Discipline Web site at http://www.uspto.gov/go/oed.Does the patent office control the fees charged by the patent attorneys or agents for their services?

With rapid advancement of the fabrication technology of a thin film transistor liquid crystal display (TFT-LCD), the LCD is largely applied in various electronic products such as a Personal Digital Assistant (PDA) device, a laptop, a digital camera, a video camera, and a mobile phone due to the fact it has advantages of smaller size, less weight, lower power consumption and low radiation. Moreover, the quality of the LCD is ceaselessly improved and the price thereof is continuously decreased since manufacturers aggressively invest in research & development and employ large-scale fabricating equipment. That promptly broadens the applied fields of the LCD.

Please refer to FIG. 1, the structure of a typical LCD panel is illustrated. Generally speaking, in the fabricating procedures of LCD panels, processes such as film depositing and lithography are applied repeatedly to fabricate considerable quantities of thin film transistors (TFT), pixel electrodes, scan lines and data lines arranged in a crisscross pattern for constructing the pixel array on a lower glass substrate 10. Then, an upper glass substrate 12 with a color filter manufactured thereon is disposed over the lower glass substrate 10. And a liquid crystal layer is inserted and sealed between the upper and lower glass substrate 12 & 10 to constitute the LCD panel.

For providing the desired voltage and signals to operate the thin film transistors of each pixel device, on the peripheral areas of the panel some circuits, chips and devices are fabricated. As shown in FIG. 1, beneath the lower glass substrate 10 a printed circuit board 14 is connected. The printed circuit board 14 has a timing controller chip and several source driver IC chips 16 thereon for electrical connecting to each pixel device via the data lines on the LCD panel. Each source driver IC chip 16 is respectively connected to display panel with a flexible bus 18 and electrical connected to the pixel devices via the circuit patterns formed on the display panel.

FIG. 4 is a schematic cross sectional view of the LCD panel illustrating the bypassing bus is connected with the WOA lines by using an anisotropic conductive film (ACF) according to the present invention;

Please refer to FIG. 2, the manner of applying a flexible printed circuits board to provide signals bypassing paths according to the present invention is illustrated. As above-mentioned, a liquid crystal display panel 50 comprises a lower glass substrate 52, an upper glass substrate 54, and a liquid crystal molecules layer placed in between these two glass substrates 52 & 54. In generally, on the lower glass substrate 52 a large number of TFTs, scan lines and data lines in a crisscross pattern are fabricated to constitute the pixel array. And beneath the upper glass substrate 54 a color filter (CF) film is fabricated so as to produce desired images via the inserted liquid crystal molecules layer after associating with the lower glass substrate 52.

Besides, for effectively operating the TFTs in the LCD panel 50, beneath the LCD panel 50 a printed circuits board (PCB) 56 is connected for transferring driving signals to the LCD panel 50 via a timing control chip (not shown) and source driver IC chips 58 on the PCB 56, and a flexible bus 60. And on the right side of the lower glass substrate 52, a narrow bar area is reserved for fabricating gate driver IC chips 62 and WOA (wire on array) lines 64. Via the WOA lines 64 defined on the lower glass substrate 52, these gate driver IC chips 62 are connected together in series.

In general, the gate driver IC chips 62 are fabricated directly on the lower glass substrate 52 by using the chip on glass (COG) technique so as to transfer scan signals to the pixel array and drive the selected pixel devices. As to the WOA lines 64 are directly defined on"the lower glass substrate 52 and disposed among those gate driver IC chips 62 so as to connect all the gate driver IC chips 62 in series. Thus, the control signals can be transferred from the PCB 56 to the pixel array of LCD panel 50 via these gate driver IC chips 62 and the WOA lines 64. And especially, via the WOA lines the control signals can be conveyed from the leading ones to the rear ones of the serial gate driver IC chips 62 to ensure that each gate driver IC chip 62 can receive the control signals.

It is noted that in FIG. 2 the bypassing bus 66 is connected with each WOA line 64 separately to connect each gate driver IC chip 62 in parallel, however, in actual practice, the connection of the bypassing bus 66 can be arbitrarily adjusted according to different condition. Especially for some sorts of LCD panels the usable area on the right side thereof maybe very small. In such cases, it is not required to make the bypassing bus 66 connect with each WOA line 64. And an option is to let the bypassing bus 66 merely connect with some selected WOA lines 64. For instance, refer to FIGS. 3A˜C, several different connecting manners are shown. In FIG. 3A, the bypassing bus 66 is just connected with the first one and the last one gate driver IC chips 62; in FIG. 3B, the bypassing bus 66 is connected with some WOA lines 64; and in FIG. 3C, two bypassing buses 66 are applied to individually connect with some gate driver IC chips 62 in parallel.

Furthermore, the bypassing bus 66 is applied to provide an extra bypass path with less resistance for overcoming the high resistance issue of the WOA lines 64, so the bypassing bus 66 can be designed with other different shapes rather than the comb shape to reduce the wiring resistance. For example, refer to FIG. 5, the bypassing bus 76 adhered onto the lower glass substrate 52 can be designed with a bar shape, and on the left edge of the bar several rectangular gaps are defined. When this bar shaped bypassing bus 76 is adhered onto the LCD panel 50, these rectangular gaps are applied to receive each the gate driver IC chip 62. As to the bulges of the bar shaped bypassing bus 76 just right cover over the WOA lines.

As shown in FIG. 6A, the alignment material 78 has a large wideness rather than the bypassing bus 76. Thus, the robot arm can conveniently clip the alignment material 78 to move the FPC board 80 over the LCD panel, and by precisely aligning and attaching procedures to adhere the bypassing bus 76 onto the LCD panel and aside the gate driver IC chips 62. After adhering the bypassing bus 76 onto the LCD panel, the alignment material 78 can be cut off along the dotted line 82 as shown in FIG. 5. Surely, for the convenience of aligning and adhering the bypassing bus 78, the alignment material 78 also can be cut firstly to remove a portion thereof as shown in FIG. 6B.