lcd module test circuit factory

Masuda T, Ajichi Y, Kubo T, Yamamoto T, Shinomiya T, Nakamura M, Shimizu T, Kasai N, Mouri H, Feng XF, Teragawa M (2009) Ultra thin LED backlight system using tandem light guides for large-size LCD-TV. In: IDW09 Proceedings, pp 1857–1860

Wakabayashi K, Mitobe K, Torigoe T (2004) Laser CVD repair technology for final yield improvement method in mass and large size TFT-LCD production process. In: IDW04 Proceedings, pp 623–624

but its left center surface is weakly pressed by an elastic 6 R. Lu et al, “3-D simulations on the tilt angle effect of IPS-LCD,” SID

material so that the glass surface partially deforms like a 7 K. Sawahata, “The development trend LCD alignment film materials,”

in Fig. 8(b) is smaller than that in Fig. 8(a). As a result, the 8 Y. Miyake et al, “Introduction of the new electrical test method for

array test system to be used for cell-gap management. (flat panel display) test group in 2002, he has

operators’ skill. This may lead to unstable inspection quality. He now leads the development of FPD test prod-

ICT test device mainly tests the performance of all components. The aim is to check if there are problems or defects for boards in production. The test object is a semi-finished product, but the FCT fixture test object is a PCBAfunctional test. FCT fixture mainly to simulate the product working environment to verify the function of boards during working conditions. ICT test device and FCT fixture both are online tests.

FCT refers to the functional test in which PCBA connects the power. It includes voltage, current, power, power factors, frequency, duty ratio, position determination, LED lighting, LED color, sound recognition, temperature measurement and control, pressure measurement and control, precision micro motion control, FLASH, and EEPROM online programming. It refers to the operating environment (excitation and load) that provides simulation against the UUT.

The earliest function tests are mainly automatic and semi-automatic. In order to simplify the design and reduce production costs, manual and semi-automatic are still used. With the technology development, to save production costs and improve production efficiency, most of the functional tests are fully automated.

You can request full PCB manufacturing Price that Rayming provide PCB,assembly, electronic components and testing, Also you can ask partial PCBA quote that you will provide some components by yourself, Our pcb assembly services is flexbile

System control center:The main parts of the full test system composed of PC, MCU, ARM, central processing. The primary functions are to control all test processes, record the contents and results of each step test, and create a final test result.

Control executive:Control executive is composed mainly of I/O. It is the execution of logical actions during the testing process. The system builds various testing environments based on the testing function.Measurement part: The measurement part is mainly composed of a special measurement board and instrument. It mainly completes the collection of various analog or digital during the test process. It is also called data collection.Data processing and output: The purpose of the final test result is to figureout how to store and output the results data. It will be advantageous for us to control thePCBA quality effectively. This is the responsibility of data processing and output.

In the PCBA batch process, it is impossible to achieve 100% running status on the equipment and human operators. PCBA are good,so it requests all kinds of test equipment and test tools at the end of production. This leads to the other types of testing, such as ICT, AOI,X-Ray, Boundary Scan, to make sure all the circuit boards according to the design of various specifications and parameters.

FCT means providing a simulated running environment (excitation and load) to a UUT, making it functional in different design situations. Then, getting a range of different design situations to improve the UUT function. In short, it is suitable to load to the UUT, and the UUT output shows whether or not the board fits the design; it is called the PCBA functional test. FCT fixture is a fixture that simulates the finished PCBA.

ICT only tests if the PCBA is connected,short-circuited, LCP value, wrong orientation diode, and other semiconductor connections. The principle is to isolate other components then test a single or series-parallel group of components individually.

FCT is different; it is a functional test. It tests PCBA key componentsor output waveform through the relevant voltage or signal and determines if the values are within the acceptable range. Do not test against components. If the component fails, the functionality will be affected.

fiberboard. They are then applied to the computer main board, LED lamp main board, LCD TV main board, communication equipment main board, and other electronic products.

According to the test board and test requirements, select relay control, embedded microcontroller control mode, PC control mode, and PLC control mode. Then select the corresponding components after the mode is determined.

11.Function, lifetime, maneuverability, esthetic should be considered when design work. To achieve stable test and long service life, Beautiful appearance and humanized operation

This part contains PC, MCU, PLC, and other central processor components. Its main role is to control the whole test process and each step of the test content for evaluation and test results. It is the brain of the whole test system.

The control execution part comprises I/O components, induction, and execution mechanism of logical actions in the test process. The system builds a variety of testing environments to achieve the testing functions.

The measurement part is mainly composed of board instruments. It mainly completes the collection of various analog or digital data in the testing process.

5.3.3. Each assembly step should be followed carefully and correctly to ensure the parallelism of the press board to the load board vertical board. This is to ensure the accuracy of the test fixture.

5.3.4. Select the correct test probe, test point normally is Pin ,Component pin using claw needle, if customers have special requirements can use other types of probe (round class). Probe contact 3.5mm-4.0mm, more test points can reduce the contact travel accordingly.

5.3.6. Press bar to choose anti-static black steel bar, choose the flat press bar in the case of not hamper testing and collision, small position can be processed into a cone type

Check the network is correctand check for open short circuits before connecting the device. If any special TP point should be connected during the test, the software should detect the short circuit.

Test for few goods or bad onesunder the test debugging system model. Verify the test results are consistent with the actual product and revise the test standard if necessary.

4.5. Check fixture stability and protection, especially special parts, such as external optical fiber, MIC, automatic card insertion device, adapter plate fixing module, pressing plate needle module, and other special switching devices.

4.13. The tightness of the casing is moderate, without any loosening phenomenon, and  the casing height is correct or not (down test compression is 2/3, up-test compression is 1/3~1/2)

4.16. Whether spare parts meet requirements and prepare the document according to the product list：Customized functional test system (including tester and fixture).

Check whether the air pressure in the appropriate range (4-6kg/cm2), the test program and fixture are correct, and the fixture arrangement is connected in order.

5. When inserting any test periphery, be sure to turn off the test fixture power to avoid damage to the test periphery. Use both hands to hold the two sides of the CPU. Align the CPU slot and insert the CPU’s golden finger from top to bottom. On the contrary, in selecting the application of both hands from the bottom up the CPU out.

8. Please pay attention to the display during the VFA test and make sure it is the correct paint and color. Also, please pay attention to whether the sound emitted by the buzzer on the board is normal.

PCB assembly testing methods are an integral part of the manufacturing process. Reputable electronics contract manufacturers (ECMs) offer a variety of PCB testing methods, but the seven main types include:

In-circuit testing (ICT) is the most robust type of PCB testing in existence. The high price reflects that -- tens of thousands of dollars, though the cost will depend on board and fixture size, among other factors.

An ICT, also known as a bed-of-nails test, powers up and actuates the individual circuitry on the board. In most cases, the test is designed for 100% coverage, but you’ll get closer to 85-90% coverage. The nice thing about ICT is that the 85-90% you get is totally free of human error.

This test involves using fixed probes laid out in a way that matches the design of the PCB. The probes checks the integrity of the solder connection. The bed of nails tester simply pushes the board down on the bed of probes to start the test. There areaccess points predesigned in the board that allows the ICT testing probes to make connections with the circuit. They put a certain amount of pressure on the connection to make sure it stays intact.

This test is for a “mature” product with very few revisions expected. If you don’t have design-for-manufacturing as part of your goal, with the proper pads on the board, you may not be able to use an in-circuit test. Unfortunately, you can’t change your mind and move to an ICT strategy halfway through production.

The test works through the use of needles attached to a probe on an x-y grid obtained from basic CAD. Your ECM programs coordinates to match the circuit board and then runs the program.

In some cases, ICT makes it unnecessary to use flying probe testing, but the PCB has to be designed to fit with the test fixture -- which means a higher initial cost. ICT can be faster and less error-prone than flying probe testing, so you might find the extra cost is worth it. While flying probe testing can be cheaper initially, it may actually be less cost-effective for large orders.

As the name suggests, burn-in testing is a more intense type of testing for PCBs. It’s designed to detect early failures and establish load capacity. Because of its intensity, burn-in testing can be destructive to the parts being tested.

Burn-in testing pushes power through your electronics, usually at its maximum-specified capacity. The power is run through the board continuously for 48 to 168 hours. If a board fails, it is known as an infant mortality. For military or medical applications, boards with high infant mortality are clearly not ideal.

Burn-in testing isn’t for every project, but there are some cases where it makes a lot of sense. It can prevent embarrassing or dangerous product launches before they reach customers.

Just remember that burn-in testing can shorten the product’s lifespan, especially if the test puts your board under more stress than it’s rated for. If few or no defects are found, it"s possible to reduce the testing limit after a shorter period to avoid over-stressing your PCBs.

X-ray testing can check elements that are usually hidden from view, such as connections and ball grid array packages with solder joints underneath the chip package. While this check can be very useful, it does require trained, experienced operators.

It does take time. If you want to get your product out the door quickly, this may not be your best choice. But from a quality and longevity standpoint, functional testing can save face and save money.

A PCB functional test verifies a PCB’s behavior in the product’s end-use environment. The requirements of a functional test, its development, and procedures can vary greatly by PCB and end product.

Figuring out what PCB testing is right for you can be a challenge; there are certainly a lot of methods! Your ECM will know which tests are right for your specific needs, so consult with them often.

And don’t forget about PCB prototyping. This essential element of product launches acts as a test in its own right, allowing you to see the real thing before your market does.

200426747 玖、發明說明： 【發明所屬之技術領域】 本發明關於一液晶顯示器（LCD)、其測試方法及其製造 方法。 【先前技術】 液晶顯示器（LCDs)為最普遍使用之手提式平面板顯示 器（FPDs) 〇 典型之液晶顯示器（LCD)包括具有場產生電極與偏光片 心一對面板，及一具有誘電性非等向性之液晶層，其介置 於一面板足間且承受由電極產生之電場。電場強度之變化 會改變液晶層之分子方位，而配列平行於或垂直於場方向 。LCD透過偏光片而令光線透過液晶層，且重新定位液晶 分子以改變光、線之偏光。$光片將偏光之變化轉換成光線 透射比之變化’且取得所需之影像。 複數閘極線及資料線分別在一具有TFTs形成於其上之 面板上’酉己置於列及行方向，像素電極即通過TFTs而連接 於閘極線及資料線。TFT係在—通過閘極線而收到—問極 信號之控制下，控制資料信號對於像素電極之傳輸。問極 信號產生於複數閘極驅動ICs(積體電路)，閘極驅㈣則自 具有或夕DC/DC轉換器之驅動電壓產生器接收一閘極 導通電壓及-閘極切斷電壓，並將其組合以在一信號控制 器之控制下產生閘極信號。資料信號係藉由將信號控制器 之影像信㈣換成類比電壓，而產生於複數資料驅動心。 信號控制器、驅動電壓產生器、等等係提供於一通常設200426747 (1) Description of the invention: [Technical field to which the invention belongs] The present invention relates to a liquid crystal display (LCD), a test method thereof, and a manufacturing method thereof. [Previous technology] Liquid crystal displays (LCDs) are the most commonly used portable flat panel displays (FPDs). Typical liquid crystal displays (LCDs) include a pair of panels with a field generating electrode and a polarizer core, and A directional liquid crystal layer is interposed between a panel foot and withstands an electric field generated by an electrode. The change of the electric field strength will change the molecular orientation of the liquid crystal layer, and the arrangement is parallel or perpendicular to the field direction. LCDs pass polarizers to allow light to pass through the liquid crystal layer, and relocate liquid crystal molecules to change the polarization of light and lines. The $ light sheet converts changes in polarized light into changes in light transmittance ’and obtains the desired image. The plurality of gate lines and data lines are respectively disposed on a panel having TFTs formed thereon in the column and row directions, and the pixel electrodes are connected to the gate lines and the data lines through the TFTs. TFT controls the transmission of data signals to pixel electrodes under the control of—received through gate lines—interrogation signals. The interrogation signal is generated by a plurality of gate driver ICs (integrated circuit), and the gate driver receives a gate-on voltage and a gate-off voltage from a driving voltage generator with a DC / DC converter, and They are combined to generate a gate signal under the control of a signal controller. The data signal is generated from the complex data-driven core by replacing the image signal of the signal controller with an analog voltage. Signal controllers, drive voltage generators, etc. are provided in a conventional device

置在面板外之印刷電路板（PCB)上，且驅動ICs配置於一設 置在面板與PCB之間之撓性印刷電路（Fpc)膜上。一1^〇〇通 苇具有一 PCBs，其中一者設於面板之上側，而另一者設於 其左側’左側者稱為閘極PCB，而上方者稱為資料pcb。 設置在閘極PCB與面板之間之閘極驅動ICs係自閘極pCB 接收信號，而設置在資料PCB與面板之間之資料驅動ICs則 自資料PCB接收信號。 此一閘極PCB可消除而僅採用資料PCb，在此例子中， 閘極側F P C膜及形成於其上之閘極驅動I c s二者之位置可 以維持。在此一閘極PCB可消除之例子中，分離式配線應 提供於資料FPC膜及面板上以及在閘極1?]?(：膜上，以利自信 號控制器、驅動電壓產生器、等等傳送信號至每一閘極驅 動1C。 再者，閘極驅動IC s可直接形成於一液晶面板組件上（玻 璃上晶片-COG-型），因此亦可消除一閘極側Fpc膜。在此 例子中’分離式配線應提供於資料FPC膜及面板上。 同時，一目視檢查（VI)測試係執行以檢查一製成lcd之 操作。針對一具有上述結構之LCD之VI測試，應在面板上 備便連接於閘極線之另一測試配線及測試墊塊，測試墊塊 之尺寸應大於一預足尺寸，例如800 μπι X 800 μιη，以確定 VI測試之充分穩定性。 惟，由於一 LCD之尺寸試著減小，測試配線及測試塾塊 之餘裕變得不足，VI測試之困難度亦因而增加。 另方面，即使有足夠餘裕可用於測試配線及測試墊塊， 87680.DOC -6- 200426747 信號配線應改變以利防止其間之干擾。用於VI測試之信號 配線之變化可能造成信號配線之線增長及配線之電阻增大 ’且據此’會對正常之信號傳輸有負面影響。因閘極線與 測試塾塊之間距離所增加之時間延遲亦會降低VI測試之 準確度。 【發明内容】 因此’本發明之動機在提供增加餘裕及減少信號延遲等 非限制性優點於一 LCD裝置，而不損害其VI測試之能力。 一種可用於本發明之舉例LCD裝置包括：一液晶面板， 其包括一具有複數第一顯示信號線之第一顯示信號配線、 具有複數第二顯示信號線且相交於第一顯示信號線之第 一顯不#號配線、各連接於其中一第一顯示信號線與其中 一第二顯示信號線之複數切換元件、及連接於切換元件之 像素兒極，第一驅動信號配線，其傳送驅動信號以用於 第或第一顯717信號線，其中第一驅動信號配線分離於第 一及第二顯示信號配線、切換元件、及像素電極，且包括 在其近端連接至此之第一墊塊；及複數第一連接線，係 設置於第一驅動信號配線與至少一部分第一顯示信號配線 ，間，且連接於至少一第一驅動信號配線及一部分第一顯 示信號配線。 在另Λ施例中，一LCD裝置進一步包含分別連接於第 一驅動信號配線之複數驅動器。 較佳為各驅動器係-晶片形式，且各驅動器係形成於液 晶面板上。The printed circuit board (PCB) placed outside the panel, and the driving ICs are arranged on a flexible printed circuit (Fpc) film placed between the panel and the PCB. A 1 ^ 〇 tong Wei has a PCBs, one of which is located on the upper side of the panel, while the other is located on the left side of the panel. "The left side is called the gate PCB, and the upper side is called the data PCB. The gate drive ICs placed between the gate PCB and the panel receive signals from the gate pCB, and the data drive ICs placed between the data PCB and the panel receive signals from the data PCB. This gate PCB can be eliminated and only the data PCb is used. In this example, the positions of both the gate side F PC film and the gate drive I c s formed thereon can be maintained. In this example where the gate PCB can be eliminated, separate wiring should be provided on the data FPC film and panel and on the gate 1?]? (: On the film to facilitate the signal controller, drive voltage generator, etc. Wait to send a signal to each gate driver 1C. Furthermore, the gate driver IC s can be directly formed on a liquid crystal panel assembly (wafer-on-glass-COG-type), so a gate-side Fpc film can also be eliminated. In this example, "separated wiring should be provided on the FPC film and panel of the data. At the same time, a visual inspection (VI) test is performed to check the operation of an LCD. For an LCD test with the above structure, the VI test should be performed at The panel is ready for another test wiring and test pad connected to the gate line, and the size of the test pad should be larger than a pre-footed size, such as 800 μm X 800 μm, to determine the sufficient stability of the VI test. The size of an LCD tries to decrease, the margin of test wiring and test pads becomes insufficient, and the difficulty of VI testing increases accordingly. On the other hand, even if there is enough margin available for test wiring and test pads, 87680.DOC- 6- 200426747 signal The wiring should be changed to prevent interference. The change of signal wiring used for VI test may cause the signal wiring to increase and the resistance of the wiring to increase "and accordingly" will have a negative impact on normal signal transmission. Because of the gate The increased time delay of the distance between the line and the test block will also reduce the accuracy of the VI test. [Summary of the Invention] Therefore, "the motivation of the present invention is to provide non-limiting advantages such as increased margin and reduced signal delay in an LCD device, Without impairing its VI testing ability. An example LCD device that can be used in the present invention includes: a liquid crystal panel including a first display signal wiring having a plurality of first display signal lines, a plurality of second display signal lines, and intersecting The first display signal # 1 wiring on the first display signal line, a plurality of switching elements connected to one of the first display signal line and one of the second display signal line, and a pixel electrode connected to the switching element, the first Drive signal wiring, which transmits drive signals for the first or first display 717 signal lines, where the first drive signal wiring is separated from the first and second Display signal wiring, switching element, and pixel electrode, and includes a first pad connected thereto at a near end thereof; and a plurality of first connection lines provided between the first driving signal wiring and at least a part of the first display signal wiring, And connected to at least a first driving signal wiring and a portion of the first display signal wiring. In another embodiment, an LCD device further includes a plurality of drivers connected to the first driving signal wiring respectively. Preferably, each driver system is- In the form of a chip, each driver is formed on a liquid crystal panel.

87680.DOC 200426747 較佳為各驅動器係直接連接於第一驅動信號配線。 在另一實施例中，一 LCD裝置進一步包含電力性且實體 性連接於液晶面板之複數撓性印刷電路膜，其中驅動器係 安裝於撓性印刷電路膜上。 在另一實施例中，一 LCD裝置進一步包含一第二驅動信 號配線，其傳送驅動信號以用於第一或第二顯示信號線， 其中第二驅動信號配線分離於第一及第二顯示信號配線、 切換元件、及像素電極，且包括一在其近端連接至此之第 二墊塊。 在此例子中，巧一驅動仏號配線與第一顯示信號配線之 間之距離較小於第二驅動信號配線與第—顯示信號配線之 間之距離。 較佳為，一LCD裝置進一步包含複數第二連接線，係設 置於第二驅動信號配線與至少另—部分第一顯示信號配線 之間，且連接於至少一第二驅動信號配線及另一部分第一 顯示信號配線。在此’較佳為第一及第二連接線係交錯設 置。 較佳為連接線之-端連接於第一顯示信號配線，且其另 一端連接於第一驅動信號配線。 八 第-連接線包含彼此呈電分離之二段，且在此例子中， 較佳為該二段分別連接於第一顯示信號配線及 號配線。 -或者依另—方式，較佳為第—連接線係電連接於第—潑 不信號配線及第一驅動信號配線。87680.DOC 200426747 Preferably, each driver is directly connected to the first driving signal wiring. In another embodiment, an LCD device further includes a plurality of flexible printed circuit films electrically and physically connected to the liquid crystal panel, wherein the driver is mounted on the flexible printed circuit film. In another embodiment, an LCD device further includes a second driving signal wiring for transmitting a driving signal for the first or second display signal line, wherein the second driving signal wiring is separated from the first and second display signals. The wiring, the switching element, and the pixel electrode include a second pad connected to the proximal end thereof. In this example, the distance between the Qiaoyi driving signal wiring and the first display signal wiring is smaller than the distance between the second driving signal wiring and the first display signal wiring. Preferably, an LCD device further includes a plurality of second connecting lines, which are arranged between the second driving signal wiring and at least another part of the first display signal wiring, and are connected to at least one second driving signal wiring and another part of the first A display signal wiring. Here, it is preferable that the first and second connecting lines are staggered. Preferably, one end of the connecting line is connected to the first display signal wiring, and the other end thereof is connected to the first driving signal wiring. The eighth-connection line includes two segments that are electrically separated from each other, and in this example, it is preferable that the two segments are connected to the first display signal wiring and the signal wiring, respectively. -Or in another way, it is preferable that the first connection line is electrically connected to the first signal wiring and the first driving signal wiring.

87680.DOC 200426747 另—實施例之一LCD裝置包含一連接於第一驅動 線之短路條。 泥配 軟佳為，第一驅動信號配線進一步包含在其中間部分連 接至此之複數第二墊塊。 同樣較佳為，第一驅動信號配線係形成與第二顯示信號 L、泉同層，第一連接線包含一連接構件，其形成與像素 電極同一層，及連接構件連接於第一驅動信號配線。 同樣較佳為，第一驅動信號配線係形成與第一顯示信號 配線同-層，i第—連接線之至少—部分係形成與顯^ 號配線同一層。 第一驅動信號配線較佳為延伸至面板之一緣部。 較佳為第一顯示信號配線傳送閘極信號以導通及切斷切 換7C件，且第二顯示信號配線通過切換元件以傳送用於像 素電極之資料信號。 第驅動^號配線較佳為傳送一閘極切斷電壓或一接地 電壓。 較，為第一_示信號配線傳送用於像素電極之資料信號 ’且第二顯示信號配線控制切換元件之導通及切斷，以利 控制資料信號對於像素電極之傳送。 —第驅5虎配線較佳為較佳為傳送灰階電壓、一時脈 信號、或一驅動電壓至驅動器。 —種LCD裝置《測試方法，該裝置包含—具有複數第一 顯示信號線之第-顯示信號配線、_具有複數第二顯示信 號線且相交於第—顯示信號線之第二顯示信號配線"各連87680.DOC 200426747 In another embodiment, the LCD device includes a shorting bar connected to the first driving line. As for the mud distribution, the first driving signal wiring further includes a plurality of second pads connected to the middle driving portion. It is also preferable that the first driving signal wiring system is formed in the same layer as the second display signal L and the spring. The first connection line includes a connecting member formed on the same layer as the pixel electrode, and the connecting member is connected to the first driving signal wiring. . It is also preferable that the first driving signal wiring is formed in the same layer as the first display signal wiring, and at least part of the i-th connection line is formed in the same layer as the display wiring. The first driving signal wiring is preferably extended to an edge portion of the panel. Preferably, the first display signal wiring transmits a gate signal to turn on and off the 7C component, and the second display signal wiring transmits a data signal for the pixel electrode through a switching element. The driving line ^ is preferably a gate cutoff voltage or a ground voltage. In addition, the data signal for the pixel electrode is transmitted for the first signal signal wiring and the on and off of the switching element is controlled by the second display signal wiring, so as to control the transmission of the data signal to the pixel electrode. — The 5th drive of the 5th drive is preferably to transmit a grayscale voltage, a clock signal, or a drive voltage to the driver. —A kind of LCD device “Test method, the device includes—the first display signal wiring having a plurality of first display signal lines, the second display signal wiring having a plurality of second display signal lines and intersecting the first display signal line’ even

87680.DOC -9- 200426747 接於其中一第一顯示信號線之複數切換元件、連接於切換 元件之像素電極、及一包括第一及第二墊塊以在其一近端 與其中間部分分別連接於第一信號配線之驅動信號配線， 可用於本發明LCD裝置之舉例測試方法包含··藉由施加一 第一測試信號至第一墊塊及一第二測試信號至第二墊塊， 以透過切換元件而驅動像素電極；及切斷驅動信號配線與 第一顯示信號配線之間之連接。 一種可用於本發明LCD裝置之製造方法包含··製造一液 晶顯示面板，其包括液晶顯示裝置且包含一具有複數第一 顯示信號線之第一顯示信號配線、一具有複數第二顯示信 號線且相又於第一顯示信號線之第二信號配線、各連接於 其中一第一顯示信號線之複數切換元件、連接於切換元件 (像素電極、一分離於第一及第二顯示信號配線且包括第 一及第二墊塊以在其一近端與其一中間部分分別連接於第 一仏唬配線之驅動信號配線、及連接於第一顯示信號配線 與驅動信號配線之複數連接線；藉由施加一第一測試信號 至第墊塊及一第二測試信號至第二墊塊，以透過切換元 件而驅動像素電極；及切斷連接線。 在另一貫施例中，一LCD裝置之製造方法進一步包含形 成-短路條以連接於第—驅動信號配線，及在製成液晶顯 示面板後去除短路條。 【實施方式】87680.DOC -9- 200426747 A plurality of switching elements connected to one of the first display signal lines, a pixel electrode connected to the switching elements, and a first and a second pad including a first end and a second pad respectively connected at its proximal end and its middle part. The driving signal wiring at the first signal wiring can be used for the example test method of the LCD device of the present invention including: by applying a first test signal to the first pad and a second test signal to the second pad, Switching the element to drive the pixel electrode; and cutting off the connection between the driving signal wiring and the first display signal wiring. A manufacturing method applicable to the LCD device of the present invention includes: manufacturing a liquid crystal display panel including the liquid crystal display device and including a first display signal wiring having a plurality of first display signal lines, a plurality of second display signal lines, and The second signal wiring which is opposite to the first display signal line, a plurality of switching elements each connected to one of the first display signal lines, connected to the switching element (pixel electrode, one separated from the first and second display signal wiring and including The first and second pads are respectively connected at a proximal end and a middle portion thereof to a driving signal wiring of the first blunt wiring, and a plurality of connecting lines connected to the first display signal wiring and the driving signal wiring; by applying A first test signal to the first pad and a second test signal to the second pad to drive the pixel electrode through the switching element; and cut the connection line. In another embodiment, a method for manufacturing an LCD device is further The method includes forming a short-circuit bar to be connected to the first driving signal wiring, and removing the short-circuit bar after the LCD panel is fabricated.

圖中揭示本發明 施’且不應拘限 87680.DOC 200426747 於本文内載述之實施例。 在圖式中，諸層及區域之尺寸及相對尺寸為求清楚而予 以加大，圖中相同之參考編號係指相同元件。可以瞭解的 元件例如一層、膜、區域、基板或面板稱為在另一 元件上時，其可直接在另一元件上或者亦可存在介置元 士匕之下，當一元件稱為”直接”在另一元件上時，則 不存在介置元件。 隨後，本發明實施例液晶顯示器、其測試方法、及製造 方法將參考圖式說明於後。 圖1係本發明實施例LCD之方塊圖，圖2係一用於本發明 貫施例LCD像素之等效電路圖。 請參閱圖1，本發明較佳實施例iLCD包括一液晶面板組 件300、連接於組件300之一閘極驅動器4〇〇及一資料驅動器 500、一連接於閘極驅動器4〇〇之驅動電壓產生器7〇〇、一連 接於資料驅動器500之灰階電壓產生器8〇〇、及一用於[(：1) 控制之信號控制器600。 液晶面板組件300包括複數顯示信號線G「Gn、DnDm， 及連接於此且實質上配置成一陣列之複數像素。在一結構 觀點上，面板組件300包括成對之一下方面板ι〇〇及一上方 面板200，及一設置於其間之液晶層3。 顯虎線Gi_Gn、Di_Dm提供於下方面板上，且其 包括用於傳送閘極信號（稱之為”掃描信號”）之複數閘極線 G 1 - G n及用於傳送貝料#號（稱之為"掃描信號”）之複數資料 線D1 -Dm ’閘極線G! -Gn貫質上延伸於列方向且幾乎相互平 87680.DOC -11- 200426747 行，而資料線Di-Dm延伸於行方向且亦幾乎相互平行。 各像素包括一連接於信號線Gi-Gn、Di-Dm之切換元件Q 及一對電容器，即連接於切換元件Q之一液晶電容器CLC及 一儲存電容器CST，儲存電容器CST可依實施例而取消。 切換元件Q提供於下方面板100上且具有三端子：一連接 於閘極線01-011之控制端子、一連接於資料線之輸入 端子、及一連接於液晶電容器CLC與儲存電容器CST二者之 輸出端子。圖2舉例說明切換元件Q做為一MOS電晶體，且 MOS電晶體係由一具有非晶矽或多晶矽通道層之TFT構成。 液晶電容器CLC具有一像素電極190之二端子於下方面板 100上及一共用電極270於上方面板200上，且設置於二電極 1 90、270之間之液晶層3在功能上做為謗電質。像素電極190 連接於切換元件Q，共用電極270覆蓋上方面板200之全部 表面且接收一共用電壓VCC)m。 不同於圖2,共用電極270可形成於下方面板100上，且在 此例子中，·二電極190、270具有直線或棒形圖案。 在功能上做為一電容器以提供液晶電容器CLC以外者電 容之儲存電容器CST包括像素電極190及一設置於下方面板 100上之分離線（圖中未示），分離線透過一絕緣物而疊覆於 像素電極190且接收一預定電壓，例如共用電壓乂^㈣。代替 於分離線，儲存電容器（：57可包括一相鄰之閘極線（此經常 稱為前一閘極線），其透過一絕緣物而疊覆於像素電極190。 為了彩色顯示，各像素藉由提供複數紅、綠、及藍色濾 色片230其中一者於像素電極190所佔用之一區域内，而呈 87680.DOC -12- 200426747 見/、本身顏色’圖2所tf之濾色片23〇提供於一面向像素電 極190足上万面板2〇〇上。另者，遽色片係在下方面板_ 上之像素電極190上或下方。 一或多偏光片（圖中未示）接附於下方面板1〇〇及上方面 板200之外表面。 復請參閱圖1 ’具有一或多DC/DC轉換器之驅動電壓產生 器700產生一用於導通切換元件Q之閘極導通電壓V。"，及 一用於切斷之閘極切斷電壓vQff。 儘菅圖中未示，一共用電壓產生器可加入，以自Dc/Dc 轉換咨之一電壓產生共用電壓（ν。。^)。 灰階電壓產生器800產生二組相關於像素透射比之複數 灰階電壓’其中-組内之灰階電壓具有一相對於共用電壓 Vcomi正極性，而另一組内者具有一相對之負極性。 同時亦稱為掃描驅動器之閘極驅動器4〇〇連接於液晶面 板組件300之閘極線〇1_(^，以致於產生閘極信號，其來自 驅動電壓產生器700之閘極導通電壓V()n與閘極切斷電壓 Voff之組合，且將閘極信號施加至閘極線Gi-Gn。 同時亦稱為源極驅動器之資料驅動器500連接於面板組 件300之資料，且將選自灰階電壓之資料信號從灰 階電壓產生器800施加至資料線Di-Dm。 “號控制器600控制閘極驅動器400及資料驅動器5〇〇。 本發明實施例在圖1、2所示之舉例說明LCD詳細結構隨 後參考圖3詳述之。 圖3係本發明實施例之一 LCD布局示意圖。 87680.DOC -13 - 200426747 如圖3所示，一 PCB 550設置於具有閘極線Gl-Gn與資料 線014111於其上之液晶面板組件3〇〇上方，電路組件諸如信 號控制器600、驅動電壓產生器7〇〇、及灰階電壓產生器8〇〇 皆提供於PCB 550上。液晶面板組件3〇〇及Pcb 550係藉由 複數資料F P C膜5 1 0而做電力性及實體性互連。 各資料FPC膜5 10備有一安裝於其上之資料驅動1(： 540及 複數資料引線520與複數閘極驅動信號線52卜524，資料引 線520連接於資料驅動1(：: 54〇之輸出端且在接觸部分€2連 接於資料線Di-Dm，及自資料驅動1(3 540傳送資料信號至資 料線Di-Dm〇 儘管圖3僅揭示四條閘極驅動信號線52 1-524以供說明， 但是其實際數量可等於或大於五條。 信號線521傳送閘極切斷電壓vQff，而信號線522傳送一 接地電壓，信號線523傳送信號，諸如垂直同步啟始信號， 及信號線524傳送信號，諸如閘極導通電壓¥。。及/或閘極時 脈信號。信號線521-524以及資料驅動IC 540係連接於PCB 550之電路組件，信號線521-524將進一步詳述於後。 除了資料FPC膜510，一不含資料驅動1(： 540之FPC膜（圖 中未不）可接附於PCB 550及液晶面板組件300。在此例子中 ’閘極驅動信號線52 1-524可提供於此另一 FPC膜上。 如圖3所示，由橫向延伸之閘極線〇厂1與縱向延伸之資 料線D!-Dm所界定之複數像素區形成一顯示區〇於面板組 件上，一用於遮阻顯示區外部光漏之黑色矩陣22〇(以陰影 線表π )提供於顯示區d周側。儘管閘極線Gi _Gn或資料線The drawing discloses the invention "and should not be limited to the embodiment described in this document. 87680.DOC 200426747 In the drawings, the sizes and relative sizes of the layers and regions are enlarged for clarity. The same reference numbers in the figures refer to the same elements. It can be understood that when an element such as a layer, film, region, substrate, or panel is referred to as another element, it may be directly on the other element or may be placed under the intermediary element. "On another element, there is no intervening element. Subsequently, the liquid crystal display of the embodiment of the present invention, a test method thereof, and a manufacturing method thereof will be described later with reference to the drawings. FIG. 1 is a block diagram of an LCD according to an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of an LCD pixel used in an embodiment of the present invention. Please refer to FIG. 1. A preferred embodiment of the present invention iLCD includes a liquid crystal panel assembly 300, a gate driver 400 and a data driver 500 connected to the module 300, and a driving voltage generated by the gate driver 400. The controller 700, a gray-scale voltage generator 800 connected to the data driver 500, and a signal controller 600 for [(: 1) control. The liquid crystal panel assembly 300 includes a plurality of display signal lines G, Gn, DnDm, and a plurality of pixels connected thereto and arranged substantially in an array. In a structural point of view, the panel assembly 300 includes a pair of lower panels ι and a The upper panel 200, and a liquid crystal layer 3 disposed therebetween. The display tiger lines Gi_Gn, Di_Dm are provided on the lower side panel, and they include a plurality of gate lines G for transmitting gate signals (called "scanning signals"). 1-G n and a plurality of data lines D1 -Dm "gate line G! -Gn for transmitting the shell material # number (referred to as " scanning signal ") extend substantially in the column direction and are almost flat to each other 87680. DOC -11- 200426747, and the data lines Di-Dm extend in the row direction and are almost parallel to each other. Each pixel includes a switching element Q and a pair of capacitors connected to the signal lines Gi-Gn, Di-Dm, that is, a liquid crystal capacitor CLC and a storage capacitor CST connected to the switching element Q. The storage capacitor CST can be cancelled according to the embodiment. . The switching element Q is provided on the lower panel 100 and has three terminals: a control terminal connected to the gate line 01-011, an input terminal connected to the data line, and one connected to both the liquid crystal capacitor CLC and the storage capacitor CST. Output terminal. FIG. 2 illustrates that the switching element Q is a MOS transistor, and the MOS transistor system is composed of a TFT having an amorphous silicon or polycrystalline silicon channel layer. The liquid crystal capacitor CLC has a pixel electrode 190 two terminals on the lower panel 100 and a common electrode 270 on the upper panel 200, and the liquid crystal layer 3 disposed between the two electrodes 1 90 and 270 functions as a dielectric. . The pixel electrode 190 is connected to the switching element Q, and the common electrode 270 covers the entire surface of the upper panel 200 and receives a common voltage VCC) m. Unlike FIG. 2, the common electrode 270 may be formed on the lower panel 100, and in this example, the two electrodes 190, 270 have a linear or rod-shaped pattern. A storage capacitor CST that functions as a capacitor to provide capacitance other than the liquid crystal capacitor CLC includes a pixel electrode 190 and a separation line (not shown) provided on the lower panel 100. The separation line is stacked through an insulator The pixel electrode 190 receives a predetermined voltage, such as a common voltage 乂 ^ ㈣. Instead of a separate line, the storage capacitor (: 57 may include an adjacent gate line (this is often referred to as the previous gate line)) which is superimposed on the pixel electrode 190 through an insulator. For color display, each pixel By providing one of the plurality of red, green, and blue color filters 230 in an area occupied by the pixel electrode 190, it is 87680.DOC -12- 200426747 see /, the color itself is shown in the tf filter in FIG. 2 The color film 23 is provided on a panel 200 facing the pixel electrode 190. In addition, the color film is on or below the pixel electrode 190 on the lower panel _. One or more polarizers (not shown in the figure) ) Is attached to the outer surface of the lower panel 100 and the upper panel 200. Please refer to FIG. 1 "The driving voltage generator 700 with one or more DC / DC converters generates a gate conduction for turning on the switching element Q Voltage V. " and a gate cut-off voltage vQff for cutting off. Although not shown in the figure, a common voltage generator can be added to generate a common voltage (ν from a voltage of Dc / Dc conversion). ^). The gray-scale voltage generator 800 generates two sets of pixel-related transmittances. Among the plurality of gray-scale voltages",-the gray-scale voltage in one group has a positive polarity relative to the common voltage Vcomi, and the other in the other group has a negative polarity. Also known as the gate driver of the scan driver 4〇〇 The gate line 〇1 _ (^) connected to the liquid crystal panel assembly 300, so that a gate signal is generated, which is a combination of a gate on voltage V () n and a gate off voltage Voff of the driving voltage generator 700, and A gate signal is applied to the gate lines Gi-Gn. A data driver 500, also called a source driver, is connected to the data of the panel assembly 300, and a data signal selected from a gray-scale voltage is applied from the gray-scale voltage generator 800 to The data line Di-Dm. "The controller 600 controls the gate driver 400 and the data driver 500. The embodiment of the present invention illustrates the detailed structure of the LCD as shown in Figs. 1 and 2, and then details it with reference to Fig. 3. Fig. 3 87680.DOC -13-200426747 As shown in FIG. 3, a PCB 550 is disposed on a liquid crystal panel assembly 300 having gate lines G1-Gn and data lines 014111 thereon. Above, circuit components such as the letter No. controller 600, driving voltage generator 700, and gray-scale voltage generator 800 are all provided on PCB 550. LCD panel components 300 and Pcb 550 are made by multiple data FPC film 5 10 Electrical and physical interconnection. Each data FPC film 5 10 is equipped with a data driver 1 (: 540 and a plurality of data leads 520 and a plurality of gate drive signal lines 52 and 524, and the data lead 520 is connected to the data driver. The output terminal of 1 (:: 54〇 is connected to the data line Di-Dm at the contact portion € 2, and transmits the data signal from the data drive 1 (3 540 to the data line Di-Dm0). Although Figure 3 only reveals four gate drivers The signal lines 52 1-524 are for illustration, but the actual number may be equal to or greater than five. The signal line 521 transmits a gate cut-off voltage vQff, and the signal line 522 transmits a ground voltage, the signal line 523 transmits a signal such as a vertical synchronization start signal, and the signal line 524 transmits a signal such as a gate on voltage ¥. . And / or gate clock signals. The signal lines 521-524 and the data driving IC 540 are circuit components connected to the PCB 550. The signal lines 521-524 will be described in detail later. In addition to the data FPC film 510, an FPC film without data driver 1 (: 540 (not shown in the figure) can be attached to the PCB 550 and the LCD panel assembly 300. In this example, the "gate driving signal line 52 1-524 It can be provided on this other FPC film. As shown in FIG. 3, a plurality of pixel areas defined by the laterally extending gate line 〇factory 1 and the longitudinally extending data line D! -Dm form a display area 〇in the panel assembly In the above, a black matrix 22o (shown by a shaded line π) for blocking light leakage outside the display area is provided on the peripheral side of the display area d. Although the gate line Gi_Gn or the data line

Di-Dmf質上在顯示區D内延伸平行於彼此，但是其一群一 群地相互靠近，如同風扇一般，以致於相鄰信號線之間之 距離變小，且因此，信號線再次幾近於平行。 四枚閘極驅動ICs 440安裝於液晶面板組件300上，且接 近於顯示區D外之其左緣部及配列於行方向。複數閘極驅 動線321、322、323&-323(1、3 24形成於閘極驅動心440附 近’ 一些閘極驅動信號線32 1、322、3 24透過鄰近於面板組 件300上緣之接觸部分C4而電連接於資料fpc膜5 10之各別 閘極驅動信號線521、522、524，且其亦透過接觸部分C3 而連接於閘極驅動ICs 440之輸入端，接觸部分C3定位於各 別驅動信號線321、322、324之支線之一端，或定位於各線 321、322、324上。線321、322之接觸部分C3直接鋪設在 線32 1、322上’因為線32 1、322具有大的線寬度，諸線32 1 、322上之接觸部分C3之尺寸可以較大於其他接觸部分C3 者。 信號線323a-323d中之最上方信號線323a係透過接觸部 分C4而連接於資料FPC膜5 10之閘極驅動信號線523，及亦 透過接觸部分C3而連接於最上方閘極動ic 440之輸入端。 其餘信號線3231)-323(1則是透過接觸部分（：3連接至相鄰之 閘極驅動ICs 440之輸入/輸出端，閘極驅動信號線32 1、322 、323&-323<1、324鋪設在鬧極驅動]^5 440下方或定位於其 外側。 相鄰於顯示區D之閘極驅動信號線321、322、323a-323d 、324中之二線321、322係透過接觸部分ci而連接於閘極 87680.DOC -15 - 200426747 線，詳言之，二信號線321、322交錯地連接於一申列之閉 極線。測試墊塊321p、322p提供於各信號線321、322之下 方端’線321、322較寬於其他線323a-323d、324，因為其 分別接收閘極切斷電壓Vcff及接地電壓。 一形成鄰近於面板組件3〇〇上緣且延伸於縱向之短路條 320係連接於閘極驅動信號線521_524及資料線，以用於切 換元件Q之保護及切換元件q之靜電釋放保護，此短路條 320可藉由芫成面板組件3〇〇後沿著一切割線£〇做緣部研 磨而消除。 儘管圖式僅揭示一短路條320及四閘極驅動信號線32 1、 322、323a-323d、324，請注意其數量可以改變。 在接觸部分C1-C4，信號線321、322、323a-323d、324 與面板組件300上之閘極線G^Gn、資料線r^-Dm及信號線 5 2卜524間之連接係由非等向性之導電層達成，容後詳述。 不同於上述實施例的是，資料驅動ICs 54〇可以安裝於液 晶面板組件300上，而不在資料FPC膜51〇上。在此例子中 ’衩數資料驅動ICs 540係沿橫向--配列於面板組件300 上’且用於自一外部裝置傳送控制信號、灰階電壓等等之 複數資料驅動信號線（圖中未示）係提供於面板組件3〇〇上 及延伸於行方向。此外，在複數資料驅動信號線之中，最 接近於資料線二線係交錯地連接於資料線 。分離之測試墊塊提供於與資料線Dl_Dm相連接之各別資 料驅動信號線之末端，連接於資料線仏七⑺之各資料驅動 仏號線傳送相同信號至所有資料驅動ICs 540，相同信號之Di-Dmf qualitatively extends parallel to each other in the display area D, but they are close to each other in groups, so that the distance between adjacent signal lines becomes smaller, and therefore, the signal lines are almost parallel again . Four gate driver ICs 440 are mounted on the liquid crystal panel assembly 300, and are located near the left edge of the display area D and are arranged in a row direction. A plurality of gate driving lines 321, 322, 323 & -323 (1, 3 24 are formed near the gate driving core 440 "Some gate driving signal lines 32 1, 322, 3 24 pass through the contact adjacent to the upper edge of the panel assembly 300 Part C4 is electrically connected to the respective gate driving signal lines 521, 522, 524 of the data fpc film 5 10, and it is also connected to the input end of the gate driving ICs 440 through the contact part C3, and the contact part C3 is positioned at each Do not drive one end of the branch lines of the signal lines 321, 322, 324, or locate on each line 321, 322, 324. The contact portion C3 of the lines 321, 322 is directly laid on the line 32 1, 322 "because the lines 32 1, 322 have large The width of the contact portion C3 on the lines 32 1 and 322 may be larger than that of the other contact portions C3. The uppermost signal line 323a of the signal lines 323a-323d is connected to the data FPC film 5 through the contact portion C4. The gate driving signal line 523 of 10 is also connected to the input end of the gate actuator IC 440 through the contact portion C3. The remaining signal lines 3231) -323 (1 is connected to the adjacent portion through the contact portion (: 3) I / O terminals of gate driver ICs 440, gate driver Signal lines 32 1, 322, 323 & -323 < 1, 324 are laid under the alarm driver] ^ 5 440 or positioned outside it. Gate driving signal lines 321, 322, 323a-323d adjacent to the display area D The two lines 321 and 322 of 324 are connected to the gate electrode 87680.DOC -15-200426747 through the contact portion ci. In detail, the two signal lines 321 and 322 are alternately connected to a closed line of an application. The test pads 321p and 322p are provided at the lower ends of the signal lines 321 and 322. The lines 321 and 322 are wider than the other lines 323a-323d and 324 because they receive the gate cutoff voltage Vcff and the ground voltage, respectively. The shorting strip 320 at the upper edge of the panel assembly 300 and extending in the longitudinal direction is connected to the gate driving signal lines 521_524 and data lines for the protection of the switching element Q and the electrostatic discharge protection of the switching element q. This shorting strip 320 It can be eliminated by forming the panel assembly 300 after grinding along a cutting line. Although the drawing only reveals a shorting bar 320 and four gate driving signal lines 32 1, 322, 323a-323d, 324, please note that the number can be changed. In the contact part C1-C4, the signal line 32 The connections between 1, 322, 323a-323d, 324 and the gate lines G ^ Gn, data lines r ^ -Dm, and signal lines 5 2 and 524 on the panel assembly 300 are achieved by an anisotropic conductive layer. Details later. Different from the above embodiments, the material driving ICs 54 can be mounted on the liquid crystal panel assembly 300 instead of the material FPC film 51. In this example, the “numerical data driving ICs 540 are horizontally arranged on the panel assembly 300” and are used to transmit control signals, gray scale voltages, etc. from an external device. ) Is provided on the panel assembly 300 and extends in the row direction. In addition, among the plural data driving signal lines, the two lines closest to the data line are alternately connected to the data line. The separate test pads are provided at the ends of the respective data drive signal lines connected to the data lines Dl_Dm, and each data drive connected to the data line 仏 七 仏 sends the same signal to all data drive ICs 540.

87680.DOC -16- 200426747 例子為時脈彳§號、來自灰階電壓產生器8 〇 〇之灰階電塵、及 驅動電壓諸如接地電壓與用於資料驅動ICs 540之供給電 壓。 前節内所述之一 LCD具有幾乎相同於文後所述實施例 LCD者之結構及線連接，不同的是資料驅動信號線及資料 線DrDm互連，以替代閘極驅動信號線321、322與閘極線 Gi-Gn之互連。 此一 LCD之操作將進一步詳述於後。 汉置於PCB 550上之信號控制器係自一外部圖形控 制器（圖中未示）接收RGB影像信號R、G、B及用於控制其 顯示之輸入控制信號，輸入控制信號可以舉例為一垂直同 步信號Vsync、一水平同步信號出乂加、一主時脈CLK、及 一資料致能信號D E。信號控制器6 〇 〇產生閘極控制信號 CONT1及資料控制信號C0NT2，且根據輸入影像信號r、g 、B及輸入控制信號以處理適用於面板組件3〇〇操作之影像 信號（R、G.、B)。隨後，信號控制器6〇〇傳送閘極控制信號 CONTi至閘極驅動器400、及傳送資料控制信號〇〇价2與 處理影像信號R，、G，、B，至資料驅動器5〇〇。 閘極控制信號C0NT1包括—告知訊框啟始之垂直同步 啟始信號STV、-控制閘極導通電壓v〇n輸出定時之閑極時 脈信號CPV、及-界定閘極導通電壓V。。持續時間之輸出致 能信號OE。資料控制信號C0NT2包括一告知水平週期啟始 之水平同步啟始信號STH、一觸發資料電壓施加於資料線 之負載m〇AD或it " -相關於共用電壓Ve_而將資料87680.DOC -16- 200426747 Examples are clock 彳 § number, gray-scale electric dust from gray-scale voltage generator 800, and driving voltages such as ground voltage and supply voltage for data driver ICs 540. One of the LCDs described in the previous section has almost the same structure and line connections as those of the LCDs of the embodiments described later, except that the data driving signal lines and the data lines DrDm are interconnected to replace the gate driving signal lines 321, 322 and Interconnection of the gate lines Gi-Gn. The operation of this LCD will be further detailed later. The signal controller placed on the PCB 550 receives the RGB image signals R, G, B and an input control signal for controlling its display from an external graphics controller (not shown). The input control signal can be exemplified as: A vertical synchronization signal Vsync, a horizontal synchronization signal output increase, a main clock CLK, and a data enable signal DE. The signal controller 600 generates a gate control signal CONT1 and a data control signal CONT2, and processes the image signals (R, G.) suitable for the operation of the panel assembly 300 according to the input image signals r, g, B and the input control signals. , B). Subsequently, the signal controller 600 transmits the gate control signal CONTi to the gate driver 400, and transmits the data control signal 00 and the processed image signals R, G, and B to the data driver 500. The gate control signal CONT1 includes-the vertical synchronization start signal STV to inform the start of the frame,-the idle clock signal CPV that controls the output timing of the gate-on voltage von, and-defines the gate-on voltage V. . Output enable signal OE of duration. The data control signal CONT2 includes a horizontal synchronization start signal STH that informs the start of the horizontal period, a load m0AD or it "which triggers the data voltage to be applied to the data line-related to the common voltage Ve_ and the data

87680.DOC -18- 200426747 以00施加資料電壓至對應之資料線D|_Dm，且供給至資料 、·泉D|-Dm〈資料信號係通過導通之切換元件Q而供給至對 應之像素。 ^用^壓VC°m與施加於一像素之資料電壓之間之差異有 如液晶電容器cLC之一充電電壓，稱之為像素電壓。液晶分 子具有依像素電壓而定之方位，且其方位決定了通過液晶 %么為cLC之光線之偏光，偏光片將光線偏光轉換成光線透 射。 藉由回歸性施加上述程序於後續之閘極線，閘極導通電 壓V〇n即在一訊框期間依序施加至各閘極線G ! ，因此每 一像素皆接收到其資料信號。 當後一訊框在前一訊框結束後才啟始時，施加至資料驅 動器500之反相控制信號Rvs即獲控制，以致於施加至各像 素之資料電壓之極性相反於前一訊框者（，，訊框反相，，）。依 據反相控制信號RVS之特徵，流過同一資料線之資料電壓 之極性可在同一訊框内變化（”線反相”），且瞬間施加之資 料電壓之極性亦可變化（”點反相”）。 此程序將進一步詳述於後。 最先收到垂直同步啟始信號STv之最上方閘極驅動Ic 440選出驅動電壓產生器700之二電壓ν〇η、V()ff中之閘極導 通電壓Von，且隨後將選出之閘極導通電壓von輸出至第一 閘極線G!。其間，閘極切斷電壓V()ff施加至所有其他閘極 線G^Gn。連接於第一閘極線G!之切換元件Q係由閘極導通 電壓V。"導通，且用於第一列之資料信號係通過切換元件q 87680.DOC -19- 200426747 =她加至卜列内所有像素之液晶電容器b及儲存電容 器 Cst。 * 列内〈電容器cLC、Cst在一預定週期内完成充電 時，最上方（即第一）閘極驅動1(：44〇將閘極切斷電舉V "施 加至第一問極線〇1，使得連接至此之切換元件q切斷°，其 並將閘極導通電壓ν〇η施加至第二閘極線g2。 當每-閘極線已依此程序至少施加以問極導通電壓v〇n 一次時，第一閘極驅動IC 44〇供給一載送信號至第二閘極 驅動1C 440，即一用於告知掃描完成之信號。 接收載送信號時，第二閘極驅動IC 44〇依上述方式對於 所有連接至此^閘極線執行掃描。當針對所有閘極線之掃 描元成時，第二閘極驅動1(： 44〇即經由信號線32化以供給 載送信號至下一閘極驅動IC 44〇。當第一閘極驅動ic 44〇 依此方式完成其掃描操作時，一訊框即為完全處理。 如上所述，面板組件300包括二面板1〇〇、2〇〇，其中設有 TFTs之下方面板1〇〇稱為”TFT面板”，圖3中之閘極驅動信 號線321、322、323a-323d、324形成於TFT面板上，此一 TFT面板之結構特性將參考圖4-7詳述於後。 圖4係一用於本發明實施例LCD之TFT面板之布局圖，其 中圖3之資料及閘極線與分別連接於閘極及資料線之接觸 邵分C1及C2之相又面積係予以放大。圖5係沿圖4之線v_v, 所取之TFT面板截面圖。圖6揭示一放大圖，用於本發明較 佳實施例之圖3之閘極驅動信號配線及短路條。圖7係沿圖6 之線Vll-Vir所取之TFT面板截面圖。 87680.DOC -20- 200426747 閘極配線121、124、129及連接部分122形成於絕緣基板 11 〇上，閘極配線及連接部分係由金屬或其他導電性材料構 成，用於閘極配線之金屬舉例有鋁（A1)或其合金、鉬（M0) 或銷鎢合金（Mo W)、絡（Cr)、及Is (Ta)。 閘極配線12卜124、129包括沿水平方向延伸之複數閘極 線1 2 1，各閘極1 24係連接於閘極124末端之各閘極線丨2丨及 閘極墊塊1 29之一邵分，以致於接收自閘極墊塊丨29以外之 掃描信號可傳送至閘極線121。連接部分122係以相反於閘 極線124之方向而自閘極墊塊129延伸。 閘極配線121、124、129及連接部分122可形成一單層， 惟，亦可形成一多層結構。在多層結構之例子中，較佳為 一層由低電阻材料組成而其他層由對於不同材料顯現良好 電力接觸特徵之材料組成，多層結構較佳為以雙層之鉻及 銘合金、或鉬（或其合金）及銘舉例說明。 閘極配線121、124、129及連接部分丨22係以一閘極絕緣 層140覆盍·，閘極絕緣層例如由氮化矽（SiNy組成。 一由半導體例如非晶矽構成之半導體層15〇形成於閘極 124上方之閘極絕緣層14〇上，歐姆接觸層163、165形成於 半導體層150上且分割於閘極124之二側，歐姆接觸層163 、165係由半導體構成，例如摻以雜質之非晶矽，雜質 例如為磷（P)。 資料配線17丨、173、175、176、179、閘極驅動信號配線 132、136、137、138、及一短路條ι3〇形成於歐姆接觸層163 、165及閘極絕緣層140上，且其係由金屬或其他導電性材87680.DOC -18- 200426747 applies a data voltage to 00 to the corresponding data line D | _Dm, and supplies it to the data, spring D | -Dm