lcd panel edid eeprom error price

Features:  1. You can program notebook lcd edid with standart programmer set 24c02 eeprom. 2. It" s designed for writing and reading edid eeprom in led ans lcd 30 and 40 pin3. You can fix whitescreen error and brightness control errors - reading the firmware with the old broken matrix and writing it in a new. 4. You can use it with tl866cs, ezp2010, skypro and many others eeprom programmers package includes:  1 x screen code chip data read linehow to use, for reference only, the lcd and programmer does not includes.

Extended Display Identification Data (EDID) and Enhanced EDID (E-EDID) are metadata formats for display devices to describe their capabilities to a video source (e.g. graphics card or set-top box). The data format is defined by a standard published by the Video Electronics Standards Association (VESA).

The EDID data structure includes manufacturer name and serial number, product type, phosphor or filter type (as chromaticity data), timings supported by the display, display size, luminance data and (for digital displays only) pixel mapping data.

DisplayID is a VESA standard targeted to replace EDID and E-EDID extensions with a uniform format suited for both PC monitor and consumer electronics devices.

EDID structure (base block) versions range from v1.0 to v1.4; all these define upwards-compatible 128-byte structures. Version 2.0 defined a new 256-byte structure but it has been deprecated and replaced by E-EDID which supports multiple extension blocks.HDMI versions 1.0–1.3c use E-EDID v1.3.

Before Display Data Channel (DDC) and EDID were defined, there was no standard way for a graphics card to know what kind of display device it was connected to. Some VGA connectors in personal computers provided a basic form of identification by connecting one, two or three pins to ground, but this coding was not standardized.

This problem is solved by EDID and DDC, as it enables the display to send information to the graphics card it is connected to. The transmission of EDID information usually uses the Display Data Channel protocol, specifically DDC2B, which is based on I²C-bus (DDC1 used a different serial format which never gained popularity). The data is transmitted via the cable connecting the display and the graphics card; VGA, DVI and HDMI are supported.

The EDID is often stored in the monitor in the firmware chip called serial EEPROM (electrically erasable programmable read-only memory) and is accessible via the I²C-bus at address 0x50. The EDID PROM can often be read by the host PC even if the display itself is turned off.

Many software packages can read and display the EDID information, such as read-edidMicrosoft Windows and the X.Org Server for Linux and BSD unix. Mac OS X natively reads EDID information and programs such as SwitchResX

E-EDID was introduced at the same time as E-DDC, which supports multiple extensions blocks and deprecated EDID version 2.0 structure (it can be incorporated in E-EDID as an optional extension block). Data fields for preferred timing, range limits, and monitor name are required in E-EDID. E-EDID also supports dual GTF timings and aspect ratio change.

Some graphics card drivers have historically coped poorly with the EDID, using only its standard timing descriptors rather than its Detailed Timing Descriptors (DTDs). Even in cases where the DTDs were read, the drivers are/were still often limited by the standard timing descriptor limitation that the horizontal/vertical resolutions must be evenly divisible by 8. This means that many graphics cards cannot express the native resolutions of the most common wide screen flat panel displays and liquid crystal display televisions. The number of vertical pixels is calculated from the horizontal resolution and the selected aspect ratio. To be fully expressible, the size of wide screen display must thus be a multiple of 16×9 pixels. For 1366×768 pixel Wide XGA panels the nearest resolution expressible in the EDID standard timing descriptor syntax is 1360×765 pixels, typically leading to 3 pixel thin black bars. Specifying 1368 pixels as the screen width would yield an unnatural screen height of 769.5 pixels.

Many Wide XGA panels do not advertise their native resolution in the standard timing descriptors, instead offering only a resolution of 1280×768. Some panels advertise a resolution only slightly smaller than the native, such as 1360×765. For these panels to be able to show a pixel perfect image, the EDID data must be ignored by the display driver or the driver must correctly interpret the DTD and be able to resolve resolutions whose size is not divisible by 8. Special programs are available to override the standard timing descriptors from EDID data. Even this is not always possible, as some vendors" graphics drivers (notably those of Intel) require specific registry hacks to implement custom resolutions, which can make it very difficult to use the screen"s native resolution.

Preferred timing mode specified in descriptor block 1. For EDID 1.3+ the preferred timing mode is always in the first Detailed Timing Descriptor. In that case, this bit specifies whether the preferred timing mode includes native pixel format and refresh rate.

The CEA EDID Timing Extension was first introduced in EIA/CEA-861, and has since been updated several times, most notably with the 861-B revision (which was version 3 of the extension, adding Short Video Descriptors and advanced audio capability/configuration information), 861-D (published in July 2006 and containing updates to the audio segments), 861-E in 2008, and 861-F which was published on June 4, 2013.

Version 1 of the extension block (as defined in CEA−861) allowed the specification of video timings only through the use of 18-byte Detailed Timing Descriptors (DTD) (as detailed in EDID 1.3 data format above). In all cases, the "preferred" timing should be the first DTD listed in a CEA EDID Timing Extension.

I"m faced with an interesting issue! One of our client Dell laptop does not show POST/Dell splash screen when powered on. Eventually, after a minute or two, the Windows login screen appears. I"ve replaced the LCD panel, updated BIOS, drained power, reseated everything possible, and even re-imaged the HD. Dell diagnostics gives me this error: LCD EDID - Unable to access EDI EEPROM, even after replacing the LCD panel. I"m beginning to suspect that the motherboard is the culprit here. Anyone seen this type of issue before?Just out of curiosity, what does Dell Support have to say about that error?

I"m faced with an interesting issue! One of our client Dell laptop does not show POST/Dell splash screen when powered on. Eventually, after a minute or two, the Windows login screen appears. I"ve replaced the LCD panel, updated BIOS, drained power, reseated everything possible, and even re-imaged the HD. Dell diagnostics gives me this error: LCD EDID - Unable to access EDI EEPROM, even after replacing the LCD panel. I"m beginning to suspect that the motherboard is the culprit here. Anyone seen this type of issue before?Just out of curiosity, what does Dell Support have to say about that error?

SOLVED! I replaced the LVDS cable, and I am now able to see the Dell splash screen and also access BIOS and PXE boot. Diagnostics no longer reports an error. It"s a beautiful day - birds are chirping, flowers are blooming, people are happy. Thank you all for the support!!!

Reading EDID data from DVI monitor EEPROM is a common use case for the Aardvark I2C/SPI Host Adapter and DVI DDC Breakout Cable. Although the following describes DVI monitor, similar steps can be used for other DVI devices. The goal of this article is to demonstrate how to read several bytes from DVI monitor EEPROM.

The DVI Monitor EEPROM I2C target address is 0x50. The DVI Monitor EEPROM EDID length is 128 byte. In this article, Aardvark adapter reads from DVI Monitor EEPROM EDID data: 128 bytes from memory address 00 I2C target address 0x50. For additional information take a look at the EDID Documentation.

This is particularly useful to insert a delay before reading the EDID of the monitor, for example if the Raspberry Pi and monitor are powered from the same source, but the monitor takes longer to start up than the Raspberry Pi. Try setting this value if the display detection is wrong on initial boot, but is correct if you soft-reboot the Raspberry Pi without removing power from the monitor.

Set this option to 0 to prevent the firmware from trying to read an I2C HAT EEPROM (connected to pins ID_SD & ID_SC) at powerup. See also disable_poe_fan.

Setting uart_2ndstage=1 causes the second-stage loader (bootcode.bin on devices prior to the Raspberry Pi 4, or the boot code in the EEPROM for Raspberry Pi 4 devices) and the main firmware (start*.elf) to output diagnostic information to UART0.

This patent application takes priority under 35 U.S.C. 119(e) to U.S. Provisional Patent Application No.: 60/620,094, filed on Oct. 18, 2004 (Attorney Docket No. GENSP128P) entitled “VIRTUAL EXTENDED DISPLAY IDENTIFICATION DATA (EDID)” by Noorbakhsh et al, which is hereby incorporated by reference herein in its entirety. This application is also related to the following co-pending U.S. patent applications, which are filed concurrently with this application and each of which are herein incorporated by reference, (i) U.S. patent application Ser. No. ______ (Attorney Docket No.: GENSP128), entitled “METHOD FOR ACQUIRING EXTENDED DISPLAY IDENTIFICATION DATA (EDID) IN A POWERED DOWN EDID COMPLIANT DISPLAY CONTROLLER” naming Noorbakhsh et al as inventors; (ii) U.S. patent application Ser. No. ______ (Attorney Docket No.: GENSP129), entitled “ACQUISITION OF EXTENDED DISPLAY IDENTIFICATION DATA (EDID) IN A DISPLAY CONTROLLER IN A POWER UP MODE FROM A POWER DOWN MODE” naming Noorbakhsh et al as inventors; (iii) U.S. patent application Ser. No. ______, (Attorney Docket No.: GENSP131), entitled “ACQUISITION OF EXTENDED DISPLAY INDENTIFICATION DATA (EDID) USING INTER-IC (IC2) PROTOCOL”, naming Noorbakhsh et al as inventors; (iv) U.S. patent application Ser. No. ______ (Attorney Docket No.: GENSP132), entitled “POWER MANAGEMENT IN A DISPLAY CONTROLLER”, naming Noorbakhsh et al as inventors; (v) U.S. patent application Ser. No. ______ (Attorney Docket No.: GENSP133), entitled “POWER SWITCHING IN A DISPLAY CONTROLLER”, naming Noorbakhsh et al as inventors; and (vi) U.S. patent application Ser. No. ______ (Attorney Docket No.: GENSP184), entitled “VIRTUAL EXTENDED DISPLAY INFORMATION DATA (EDID) IN A FLAT PANEL CONTROLLER”, naming Noorbakhsh et al as inventors each of which are incorporated by reference in their entireties for all purposes.. FIELD OF THE INVENTION

With computers, the Basic Input Output System (BIOS) queries the port of a computer to determine whether a monitor is present. If a monitor is present, the BIOS downloads standardized data that is typically contained at a read only memory (ROM) within the monitor. This standardized data is typically referred to as an Extended Display Identification Data (EDID) that contains information relating to the monitor that includes such information as the type, model, and functionality of the monitor. Typically, the BIOS contains a table that lists all of the various monitors that are supported by the computer. When a monitor is connected to the port, the BIOS reads selected information from the EDID and compares the EDID to the BIOS stored monitor data. The standard protocol requires the BIOS to read the monitor"s information even when the monitor is powered off. In this case, a small amount of power is supplied by the computer through the monitor connector to the monitor to run and access the EDID storage device.

If a match between the EDID and the BIOS stored monitor data is found, the computer system is configured to utilize this particular type of monitor and its capabilities. For instance, if the monitor has a volume control or a sleep button, the computer is configured to support this functionality. However, if the information from the EDID does not match the BIOS stored monitor data, then the computer assumes that it is communicating with a “legacy” monitor. A legacy monitor is a term that refers to a monitor having basic functionality, such as a relatively older, outdated monitor. Thus, the BIOS configures the computer into a default configuration to operate with a legacy monitor.

Presently, a DDC monitor (Display Data Channel) includes a storage device, such as an EEPROM, that stores EDID regarding the capabilities of the monitor, such as the monitor"s resolution and refresh rates. The EDID format is a standard data format developed by VESA (Video Electronics Standards Association) to promote greater monitor/host computer compatibility. At the present time, the current EDID format is described in Appendix D of Display Data Channel (DDC.TM.) Standard, version 1.0 revision 0, dated Aug. 12, 1994. For a personal computer utilizing a DDC monitor, the system software accesses the DDC related EDID that is stored within the monitor. The system software also determines the type of video controller that is installed in the system. The video controller is used to control and configure the video data sent to the monitor. The system software then compares the refresh rate obtained from the DDC monitor to the capabilities of the video controller to determine the proper refresh rate to set at the video controller, which in turn controls the monitor.

Typically, EDID is display information accessible to the host even when the monitor is powered down. In monitors that support a “dual interface” (both analog and digital connectors supported), there are typically two separate standard EDID ROM devices, located on the flat panel controller board, that store the analog and digital EDID. The EDID is accessed via dedicated DDC bus. In the conventional dual panel flat panel controller design, the two EDID ROM devices, reside on flat panel controller, are powered from the host power supplies with analog cable (VGA DDC cable) for analog EDID ROM, and digital cable (DDC_DVI cable) for digital EDID ROM. The cost of having two EDID ROM devices on flat panel controller board is expensive.

With the current cost pressure market, there is a need for a solution to support the EDID through DDC ports without having two separate EDID ROM devices. Unfortunately, however, by providing a single memory device for storing both the EDID as well as executable instructions and data for an on-board processor, potential conflicts between data acquisition requests can cause substantial performance efficiency and operational problems.

Therefore, what is desired is a method that provides arbitration between conflicting memory access requests for the single on-board memory that stores both EDID and processor related executable instructions and data. SUMMARY OF THE INVENTION

A method for acquiring EDID from a single memory device in an EDID compliant display controller by a host device coupled thereto by way of a requesting port is described.

In an EDID compliant display controller having a processor arranged to process executable instructions and associated data, a memory device for storing the executable instructions, the associated data, and extended display information data coupled to the processor, and a number of data ports any of which can request EDID from the memory device independent of the processor, a method of arbitrating memory device access requests between the processor and a requesting data port by an arbitration circuit. The method includes generating a memory access request by the requesting data port, granting access to the memory device by the arbitration circuit, reading EDID from the memory device to a data buffer, storing the read EDID in the data buffer, reading some of the stored EDID by the requesting data port, generating a processor memory access request by the processor, if the data buffer is determined to be full, then granting the processor memory access request, and if the data buffer is determined to be almost empty, then granting access to the requesting port until the data buffer is determined to be full.

In another embodiment, computer program product for arbitrating memory device access requests between the processor and a requesting data port by an arbitration circuit in an EDID compliant display controller having a processor arranged to process executable instructions and associated data, a memory device for storing the executable instructions, the associated data, and extended display information data coupled to the processor, and a number of data ports any of which can request EDID from the memory device independent of the processor is described. The computer program product includes computer code for generating a memory access request by the requesting data port, computer code for granting access to the memory device by the arbitration circuit, computer code for reading EDID from the memory device to a data buffer, computer code for storing the read EDID in the data buffer, computer code for reading some of the stored EDID by the requesting data port, computer code for generating a processor memory access request by the processor, computer code for granting the processor memory access request if the data buffer is determined to be full, computer code for granting access to the requesting port until the data buffer is determined to be full if the data buffer is determined to be almost empty, and computer readable medium for storing the computer code.

In another embodiment, a display controller coupled to a display device by way of a display interface and to a host device by way of a number of data ports is described. The display controller includes a processor arranged to process executable instructions and associated data, a single memory device for storing the executable instructions and associated data and EDID corresponding to the display device that is always available for access by the data ports and/or the processor regardless of a power state of the display controller, a data buffer for storing EDID read from the memory device, and an arbitration circuit for arbitrating memory device access requests between the processor and a requesting data port wherein when the data buffer is not almost empty, then the arbitration circuit grants the processor access to the memory wherein when the data buffer is almost empty, then the arbitration circuit grants only the requesting data port access to them memory so as to replenish the data buffer with read EDID. BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 5B shows a flowchart detailing a process for acquiring extended display identification data (EDID) in a video controller having a processor for processing executable instructions and associated data and a number of data ports in accordance with an embodiment of the invention.

FIG. 5C shows a flowchart that details a process for arbitrating the acquisition of extended display information data (EDID) in accordance with an embodiment of the invention.

FIG. 5D shows a flowchart that details a process for the acquisition of EDID using inter-IC (IC2) protocol in accordance with an embodiment of the invention.

A DDC monitor (Display Data Channel) includes a storage device, such as an EEPROM, that stores EDID regarding the capabilities of the monitor, such as the monitor"s resolution and refresh rates. In monitors that support a “dual interface” (i.e., where both analog and digital connectors supported), there are typically two separate standard EDID ROM devices, located on the flat panel controller board that store the analog and digital EDID, respectively. In addition to the EDID ROM devices, monitors also include a monitor controller that itself includes a processor having associated program memory storage configured as a programmable ROM device typically arranged as a serial peripheral interface (SPI) flash serial ROM. SPI Flash ROM is required on FLAT Panel Controller board to keep essential firmware routine of controlling panel in itself. These routines will be called by our on-chip micro-controller to execute necessary commands at certain time. It should be noted that a serial peripheral interface (SPI) is an interface that enables the serial (i.e., one bit at a time) exchange of data between a number of devices (at least one called a master and the others called a slave) that operates in full duplex mode. By full duplex, it is meant that data can be transferred in both directions at the same time. The SPI is most often employed in systems for communication between the central processing unit (CPU) and peripheral devices. It is also possible to connect two microprocessors by means of SPI.

With this in mind, the invention takes advantage of any unused portion(s) of the processor memory (such as the SPI flash serial ROM) to store the EDID thereby eliminating the costly use of extraneous memory devices to store EDID. In this way, by using the SPI Flash ROM already available to the processor to store the EDID, the invention eliminates the costs of having separate ROMs that were heretofore dedicated to storing the EDID only. In this way, the EDID is made available to the DDC ports (both analog and digital, if necessary) without having two separate EDID ROM devices. The invention provides a method that provides arbitration between conflicting memory access requests for the single on-board memory that stores both EDID and processor related executable instructions and data.

The invention will now be described in terms of a display controller circuit. It should be noted that although the display controller is described in terms of a flat panel display controller suitable for use in any number and kind of flat panel display monitors, the inventive controller circuit is suitable for any type display deemed appropriate. Accordingly, the flat panel display described herein includes liquid crystal display (LCD) type monitors suitable for use with computers and any other device requiring a display.

FIG. 1 shows a system 100 that includes an implementation of an inventive display controller 102 in accordance with an embodiment of the invention. As shown, the display controller 102 includes a processor 104 coupled to a memory device 106 in the form of an SPI-ROM 106 arranged to store both the EDID associated with a display 107 at specific memory locations separate and distinct from those memory locations 109 to store executable instructions and associated data processed by the processor 104. In the described embodiment, the system 100 also includes a number of data ports 108 that provide a transmission link between an external video source 110 (such as a computer or PC host) and the display controller 102. Generally speaking, the system 100 can include any number and type of data ports 108, however, for sake of this discussion, the system 100 is taken to be a dual interface type system that includes a Display Data Channel (DDC) type digital port (referred to as DDC-DVI port 108 a) and a DDC analog data port (referred to as DDC-VGA port 108b). The display controller 102 is coupled to the video source 110 by way of a cable 112 using the DDC-VGA port 108 bfor analog displays and the DDC-DVI port 108 afor digital displays. It should be noted that the DDC standard is a standard that defines a communication channel between a monitor and a display adapter included in a video source to which it is connected. The monitor uses this channel to convey its identity and capabilities to the display adapter.

In the described embodiment, the SPI-ROM 106 is partitioned to include a virtual EDID portion 114 that in turn is partitioned into an analog EDID portion 116 used to store analog display data and a digital EDID portion 118 used to store digital display data. In a particular implementation, the analog EDID portion 116 spans memory locations 000-100 whereas the digital EDID portion 118 spans memory locations 101-1FF but can, of course, be arranged in any manner deemed appropriate.

A portion of the controller 102 is partitioned into what is referred to as a bridge section 120 that acts as a bridge between the DDC-VGA port 108 band the DDC-DVI port 108 aand the SPI Flash ROM 106. (The bridge section 120 is described in more detail below with reference to FIG. 2). It should be noted, that the bridge section 120 also includes an analog portion 122. During operation, any EDID read request from one of the ports 108 is acted upon by the bridge section 120 by accessing that portion of the ROM 106 that stores the appropriate EDID (portion 116 for analog data and portion 118 for digital data). The bridge section 120, in turn, passes the data read from the SPI Flash ROM 106 back to the requesting port.

In the described embodiment, the controller 102 conforms to the Inter-IC bus (I2C) protocol that describes a communication link between integrated circuits having 2 active bi-directional wires called SDA (Serial DAta line) and SCL (Serial CLock line) and a ground connection. Every device connected to the I2C bus has its own unique address that can act as a receiver and/or transmitter, depending on the functionality. For example, an LCD driver is only a receiver, while a memory or I/O chip can be both transmitter and receiver.

Accordingly, during an I2C burst read, the bridge section 120 converts each byte of EDID related data to serial bits of information and passes it over a 2-wire I2C bus of the requesting DDC port. During what is referred to as OFF_Mode, (during which an on-board power regulator 124 is OFF as detected by the analog portion 122) power from an external power supply 126 is supplied to the controller 102 and the SPI-ROM 106 by way of either of an active one of the DDC ports (i.e., DDC-DVI port 108 aor DDC-VGA port 108 b) via the cable 112 and its associated channel as shown in FIG. 3. In this way, even though the power regulator 124 included in the controller 102 is powered off, the bridge section 120 and the ROM 106 still receive sufficient power to provide the necessary EDID during boot-up. During a power switching transition (i.e., between the OFF_MODE when the on-board power regulator 124 is off and the ON_MODE when the on-board power regulator 124 is on, and vice versa) the analog portion 122 senses when the on-board power regulator 124 is switched from off to on, and vice versa. During the OFF-mode, both the bridge section 120 and the SPI FLASH ROM 106 are both supplied power by one or the other of the DDC ports 108 by way of the cable 112. In the described embodiment, the power supply 126 acts to provide power through two branches of cascaded diodes 302 shown in FIG. 3 (it should be noted that for simplicity, only one of the connectors is shown). In order to avoid latch up problems in the Off_Mode (when essentially the only portion of the controller 102 that is powered is the bridge section 120) digital logic in the bridge section 120 is set to known state.

It should be noted that during a power transition from OFF to ON (i.e., when the power regulator 124 is turned on) any unfinished EDID read cycle is allowed to continue to the end of its cycle. In the context of this discussion, an unfinished EDID read cycle is that situation when the requesting DDC port is reading the EDID from the ROM 106 and the I2C STOP condition has not reached yet. During the period of time required to complete the EDID read operation, the controller 102 waits for the end of the unfinished EDID read cycle before switching to the On Mode for any subsequent EDID read request. During the time when the on-board power regulator 124 is turned on (On-Mode), the bridge section 120 arbitrates between service requests of the processor 104 for other client devices and EDID read requests from the ports 108 to the SPI FLASH ROM 106.

An auto activity detection circuit 128 (described in more detail below) located in the analog portion 122 of the bridge section 120 is designed to detect when the power regulator 124 in the controller 102 is powered on or off. In the described embodiment, the detecting is based upon a determination of a current TCLKactivity, where TCLKis flat panel controller internal clock. For example, in the case where the TCLKactivity indicates that an on-board crystal clock is active, then the power regulator 124 is determined to be on, whereas, a low TCLKactivity indicates that the power regulator 124 is determined to be off.

Since there is a limited power budget during the Off Mode, an RC based low frequency clock is activated to drive the bridge circuit 120 and an SPI_Flash ROM clock when the on-board power regulator 124 is off. However, during the On Mode the low frequency clock is turned off and the on-board crystal clock is activated since power for both the SPI_Flash ROM 106 and the bridge circuit 120 is then provided from the on-board power regulator 124. In this way, by seamlessly switching clocks, no glitch or malfunction during the EDID read or flat panel controller operation is likely to occur.

During the power-off mode, the power required for the virtual EDID operation is generated by the power supply 126 and provided by way of the cables 112. However, in the power on mode, the current requirement would increase since the controller 102 would be operating at a higher clock frequency. In this situation, the cable 112 would not be able to sustain the necessary current and, therefore, it is necessary to switch from the cable 112 to the onboard power supply 124. However, there are two conditions that need to be met to enable this switching. In any display product, there is a requirement for a reference clock (TLCK) that can be generated with internal oscillator, external oscillator or clock source. The presence of this clock indicates that the chip is in power-on mode. The auto activity detection circuit 128 looks at this the clock signal TCLKand charges a capacitor based on whether it is toggling or low. The capacitor voltage drives an amplifier or inverter and causes a logic state change if it exceeds the threshold voltage of the amplifier or inverter. For example, in the display products, there is generally a microcontroller interface and it is possible to change the register bits once the controller is in power on mode. As explained above, the TCLKsignal itself is sufficient to do the power switching. To make the system more robust, in addition to the TCLK, a signal from the register bits is detected, which in the power off mode is low, or “0”. Once the power is on, however, this bit can be programmed to high, or “1” using low frequency mode. The logic combination of this bit and TCLK(act and/act) is used to do the power switching.

Since the described controller 102 is I2C compliant, the I2C protocol specification states that any circuit connected to an I2C bus that initiates a data transfer on the bus is considered to be the bus master relegating all other circuits connected to the bus at that time be regarded as bus slaves. In the I2C protocol, when the slave cannot keep up with a master read or write command, the slave holds the bus (i.e., stalling the bus activity) by holding the I2C clock (one of two wire I2C) to low (referred to as clock stretching). Accordingly, since the controller 102 is slaved to the video source 110 (such as a PC host) as the master, when the PC host 110 wants to read EDID from the ROM 106 through either the DDC-VGA 108 bor DDC-DVI port 108 a,the VESA standard does not allow the controller 102 to hold either of the busses connected to the ports 108. In another words, the VESA standard assumes that the ROM 106 is always available and PC host 110 can read EDID from the ROM 106 through one or the other of the DDC ports 108. Therefore, in order to conform to the VESA standard and still remain I2C compliant, an arbitration circuit 130 provides for execution of both an EDID read request as well as request from other client devices inside controller 102 that require reading the ROM 106. In a particular embodiment, the arbitration scheme utilizes a FIFO 132 that holds EDID data read from ROM. While the requesting VGA DDC port reads the FIFO 134 (byte by byte), each byte of data is sent through the requesting DDC port (serial I2C port) bit by bit. When the FIFO 132 is almost empty, the FIFO 132 is again given access to the ROM 106 in order to satisfy any pending EDID read requests while other requesting clients are interrupted until such time as the FIFO 132 is replenished with appropriate data.

FIG. 2 shows a bridge circuit 200 in accordance with an embodiment of the invention. It should be noted that the bridge circuit 200 is a particular implementation of the bridge circuit 120 shown and described in FIG. 1. The bridge circuit 200 includes a DDC PORT controller block 202 (202 aassociated with port 108 aand 202 bassociated with 108 b) for each of the DDC ports 108. When the power regulator 124 is powered off (Off Mode), power is supplied by either of DDC ports cable (VGA/DVI), feeding power to the bridge section of the chip and the SPI_FLASH ROM 106. During this time, one of the DDC PORT controller blocks 202 (VGA/DVI) is responsible for sending an EDID read request to an SPI state machine (SPI_SM) controller 204. The SPI_SM controller 204 acts upon the EDID read request to read requested data from the appropriate portion of the SPI Flash ROM 106 and pass the read data back to the appropriate DDC_PORT controller 202. The DDC_PORT controller 202, in turn, converts each byte of EDID related data to serial bits of information and passes it over the I2C bus of active DDC port 108.

As discussed above, in the I2C protocol, when the slave device cannot keep up with a master read or write command, the slave device can hold the bus (more like stalling the bus activity) from doing any more activity by holding I2C clock (one of two wire I2C) to low (clock stretching). In the described embodiment, the flat panel controller 102 is the slave device and PC host is the master. When the PC host wants to read EDID data from the ROM 106 through either the VGA DDC port 108 bor DVI DDC port 108 a,the VESA standard presumes that the ROM 106 is always available (i.e., the PC host can read EDID data from it through the DDC port 108). Therefore, the VESA standard does not provide for the slave device (controller 102) to hold the requesting DDC port 108 when data is not ready. Therefore, in order to maintain compliance with the VESA standard, the arbitration block 130 provides an arbitration service that enables processor 104 to keep up with both an EDID read request rate, as well as request from other circuits inside flat panel controller 102 demanding access to the ROM 106.

In order to facilitate arbitrating ROM access requests, the FIFO 134 (which in this case is 8 bytes deep) holds EDID read from ROM 106. The requesting DDC port interface block reads the requested EDID from the FIFO 132 (byte by byte) and sends each byte of data through the requesting DDC port bit by bit to the PC host 110. When the FIFO 132 is almost empty, the processor 104 is flagged indicating that the processor 104 may be required to interrupt other requesting client devices in order to fill the FIFO 132 with additional requested EDID. In this way, the requesting DDC port is provided access to the ROM 106 as needed without the need to resort to clock stretching thereby maintaining compliance to the VESA standard. When the FIFO 132 is replenished, the processor 104 releases the flag and any other requesting client is permitted access to the ROM 106.

FIG. 4 shows an exemplary auto activity detection circuit 400 in accordance with an embodiment of the invention. The auto activity detection circuit 400 is designed to detect when the power regulator in the controller is powered on or off. When the power regulator is powered on, the TCLKis toggling otherwise, the TCLKis 0 when the power regulator is powered off. The auto activity detection circuit 400 will charge the capacitor C1 when the TCLKis toggling and the node N1 will charge to high voltage causing node N2 to be high. If the iCORE_DETECT is set to high from the register control, node N3 will be high resulting in an output ACT signal to be high indicating that the controller power is on. The ACT can also be set to ONE by way of the iEDID_EN_PAD enable signal (which is a bond option signal).

FIG. 5A shows a flowchart detailing a process 500 in accordance with an embodiment of the invention. The process 500 begins at 502 by a determination if the flat panel controller (FPC) is powered on. If the controller is determined to be powered on, the a DDC port state machine is granted access to the virtual EDID ROM at 504 and at 506, the requested EDID is read from the virtual EDID ROM and at 508 a determination is made whether or not the DDC port state machine is busy. Returning to 502, if, in the alternative, the controller has been determined to be powered off, then control is passed directly from 502 to 508 where if the DDC state machine is determined to be busy, then control is passed back to 506, otherwise, the controller state machine is granted access to the ROM at 510. At 512, a determination is made if other ports are requesting access to the ROM. If no other ports are requesting access, then the controller services all requests at 514, otherwise, at 516 the controller services all requests and provides any requesting port access to the ROM.

FIG. 5B shows a flowchart detailing a process 518 for acquiring extended display identification data (EDID) in a video controller having a processor for processing executable instructions and associated data and a number of data ports in accordance with an embodiment of the invention. The process 520 begins at 522 by activating an on-board power supply and at 524 disconnecting an off-board power supply arranged to provide power to the memory device when the on-board power supply is activated. Next at 526 providing power from the on-board power supply to a memory device used to store the EDID and the executable instructions and associated data and at 528 providing power from the on-board power supply to an on- board clock circuit capable of providing a high frequency clock signal. At 530, providing the high frequency clock signal from the on-board clock circuit to the memory device, and at 532 if a memory read operation was in progress when the on- board power supply was activated, then completing the memory read operation at 534.

FIG. 5C shows a flowchart that details a process 536 for arbitrating the acquisition of extended display information data (EDID) in accordance with an embodiment of the invention. The process 536 begins at 538 by generating a memory access request by the requesting data port and at 540, granting access to the memory device by the arbitration circuit. At 542, reading EDID from the memory device to a data buffer and at 544 storing the read EDID in the data buffer and at 546 the requesting port reads some of the stored EDID by the requesting data port. At 548, generating a processor memory access request by the processor and at 550, a determination is made whether or not the data buffer is determined to full. If it is determined that the data buffer is full, then at 552 the processor memory access request is granted, and in any case, at 554 the requesting port continues to read from the buffer. At 556, a determination is made whether or not the buffer is almost empty and if it is determined to be almost empty, then at 558, the requesting port is granted access to the memory, otherwise, the requesting port continues to read data from the buffer.

FIG. 5D shows a flowchart that details a process 560 for the acquisition of EDID using inter-IC (IC2) protocol in accordance with an embodiment of the invention. The process 560 begins at 562 by generating an EDID read request by the host device and at 564 passing the EDID read request by way of the requesting port to the memory device. At 566, the requested EDID is transferred from the memory device to a data buffer while at 568, memory access is granted to the processor, and at 570 reading the requested EDID from the buffer in a byte by byte manner; and sending each byte of data through the requesting data port bit by bit to the host device at 572. In this way, the requesting data port is provided access to the memory device as needed without clock stretching thereby maintaining compliance to the VESA standard.

After replacing the motherboard, i now have a different issue where i can not get a display on the LCD. I am able to hook up an external LCD and get the display to work on it.

I was able to run the Dell diagnostics and im getting an error code of 0413. The code means LCD cable not detected. I reseated the cable and still have the same issue. The cable and connector look fine and none of the pins look damaged.

Im getting what appears to be 2 different BIOS beep codes when first starting the laptop. The first one is a series of 3 short beeps, followed by 2 quick beeps and then repeats. This happens several times and then i get 8 beeps which repeat several times as well. Beep codes stop and it does boot to the Windows 7 login screen on the external LCD.

So something more than the LCD cable seems to be at fault here. Looking at the Service Manual from here: M5030 Service Manual the display cable does attach to the back of the LCD panel and is replaceable. Before i jump through the hoops of getting it replaced, i thought i would get someone elses opinion.