lcd panel side cof data factory

COF Points Detect Data for LCD LED TV Panel Part 1 Very Soon Upload Parr2 for more details please visit our website. Subscribe our channel for more informat...

COF IC is the only IC that connects TV PANEL with the T-CON board physically. SO today in this article I will explain full information about COF IC and also tell you how to get and download COF IC datasheet. If you want to know the process of COF IC downloading, read this article very carefully.

You can not COF IC data from the official site of any number COF IC. You already know about me and here I’ll give you Panel COF data downloading link which I get while repairing. And if you do not get your COF data which you need to comment down below. I will update you on the COFdatasheet as soon as possible.

If you are an Electronics technician especially LCD/LED, Definitely you have to know about COF IC. How to work COF IC and working principle of this IC. Also you have to know the voltage value of this IC. If you are interested to know about COF IC voltage value click here and know how many types of voltage has present in this IC.

Every single panel have their own development and manufacturing COF IC. I make a video on this topic and post an article, If you want to see click here.

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At present, in order to save cost, some liquid crystal television (LCD TV) manufacturers integrate a control board (or called as a TCON board) into a system board (or called as a main board) while designing. Therefore, it is not necessary to purchase control boards when purchasing LCD panels. This kind of product is called TCONLESS TV product.

In one application, a protocol of image data transmission between a system board and an LCD panel of a TCONLESS TV product is a P2P (Point-To-Point) interface protocol, so as to realize high-speed signal transmission. There are many kinds of P2P protocols currently, such as iSP (Integrated-Stream Protocol), USI-T(Unified Standard Interface for TV), CHPI(China BOE Point-to-Point Interface), CSPI(China Star Point-to-Point Interface), CMPI(Clock Embedded Point-to-Point Interface), CEDS(Clock Embedded Differential Signal), etc., which are applied to different LCD panel manufacturers.

With different P2P protocols, an image data format and a training method between TX (Transmit) and RX(Receive) will be different, which will result in different designs of system boards according to different P2P protocols, and the system boards cannot adapt to a variety of P2P protocols, and are of poor versatility. SUMMARY

In order to overcome at least part of defects and deficiencies in the prior art, a display device provided in an embodiment of the disclosure includes: a display panel including a gate driving circuit and a source driving circuit, a horizontal direction circuit board (XB board) including a driving circuit board assembly, and a system board including a system-on-chip and a second connector electrically connected with the system-on-chip; the driving circuit board assembly includes a display control circuit and a first connector, the display control circuit is electrically connected with the gate driving circuit, the source driving circuit and the first connector, and the first connector includes voltage supplying pins, point-to-point (P2P) interface pins and serial peripheral interface (SPI) pins; the second connector is electrically connected with the first connector through a connecting member; the system-on-chip is configured for acquiring a type identification signal transmitted by the connecting member and identifying a P2P interface type according to the type identification signal, and further transmitting corresponding P2P data to the connecting member according to the P2P interface type.

An interface type selection method of a display device provided in an embodiment of the disclosure, includes: acquiring a type identification signal and identifying a P2P interface type according to the type identification signal; and transmitting a corresponding P2P data according to the P2P interface type; wherein the P2P interface type includes one or more of an Integrated-Stream Protocol (iSP) interface, an Unified Standard Interface for TV (USI-T), a China BOE Point-to-Point Interface (CHPI), a China Star Point-to-Point Interface (CSPI), a Clock Embedded Point-to-Point Interface (CMPI) and a Clock Embedded Differential Signal (CEDS) interface.

In an embodiment of the disclosure, the acquiring a type identification signal and identifying a P2P interface type according to the type identification signal, includes: acquiring a direct current (DC) voltage level data transmitted by a preset pin; comparing the DC voltage level data with the preset value stored in advance to and identifying the P2P interface type corresponding to the DC voltage level data; the DC voltage level data is a type identification signal.

An interface type selection method of a display device provided in an embodiment of the disclosure; the display device includes: a display panel including a gate driving circuit and a source driving circuit; a horizontal direction circuit board (XB board) including a driving circuit board assembly, a system board including a system-on-chip and a second connector electrically connected with the system-on-chip; the driving circuit board assembly includes a display control circuit and a first connector, the display control circuit is electrically connected with the gate driving circuit, the source driving circuit and the first connector, and the first connector includes voltage supplying pins, point-to-point (P2P) interface pins and serial peripheral interface (SPI) pins; the second connector is electrically connected with the first connector through a connecting member; the interface type selection method is performed by the system-on-chip and includes: acquiring a type identification signal and identifying a P2P interface type according to the type identification signal; and transmitting a corresponding P2P data according to the P2P interface type; the P2P interface type includes one or more of an Integrated-Stream Protocol (iSP) interface, an Unified Standard Interface for TV (USI-T), a China BOE Point-to-Point Interface (CHPI), a China Star Point-to-Point Interface (CSPI), a Clock Embedded Point-to-Point Interface (CMPI) and a Clock Embedded Differential Signal (CEDS) interface

The following description of the embodiments is referred to the additional schematic views to illustrate specific embodiments of the disclosure that can be implemented. Directional terms mentioned in the disclosure, such as "up", "down", "front", "back", "left", "right", "inside", "outside" and "side surface" are only directions referring to the additional schematic views. Therefore, directional terms are used to explain and understand the disclosure, rather than to limit the disclosure.

The drawings and illustrations are considered to be illustrative in nature rather than restrictive. In the drawings, units with similar structure are represented by a same label. In addition, for the sake of understanding and easy description, size and thickness of each unit shown in the drawings are shown arbitrarily, but the disclosure is not limited to this.

As shown in FIG. 1, an active matrix display device 10 provided in an embodiment of the disclosure includes: an active matrix panel, a system board 13 and a connecting member CL1. The active matrix panel is, for example, a liquid crystal panel, which includes a display panel 111 and a XB board which includes a source driving circuit board assembly. The active matrix display device 10 in the embodiment is, for example, a TCONLESS-type LCD TV, but the embodiment of the disclosure is not limited to this.

Specifically, the display panel 111 includes a display area 1111 and a gate driving circuit 1113 and a source driving circuit 1115 electrically connected with the display area 1111. The display area 1111 is provided with a plurality of data lines DL, a plurality of gate lines GL and a plurality of pixels P electrically connecting with data lines DL and gate lines GL; each pixel P is located at an intersection of a corresponding gate line GL and a corresponding data line DL. The gate driving circuit 1113 is for example a one-sided GOA (Gate-On Array) circuit or a bilateral GOA circuit. For a one-sided GOA circuit, it is located in a peripheral area which is on one side of the display area 1111, such as a left side or a right side; for a bilateral GOA circuit, it is located in a peripheral area of the display area 1111 and is arranged on two opposite sides of the display area 1111.The gate driving circuit 1113 is electrically connected to the gate lines GL in the display area 1111 and is configured for providing gate driving signals to the plurality of gate lines GL in the display area 1111. The source driving circuit 1115 includes, for example, a plurality of COF-type source drivers 1115S, such as twelve COF (Chip-On-Flex) source drivers 1115S shown in FIG. 1. The plurality of COF source drivers 1115S are electrically connected to the data lines DL in the display area 1111 and are configured for providing image data signals to the plurality of data lines DL. More specifically, a single COF-type source driver 1115S includes, for example, a flexible circuit board and a source driver IC arranged on the flexible circuit board.

As a circuit board assembly connected with the source driving circuit 1115, the source driving circuit board assembly includes two driving circuit boards 113a and 113b. The two driving circuit boards 113a and 113b are arranged on one side of the display panel 111 along the horizontal direction of FIG. 1, that is, as a horizontal direction driving circuit board (commonly known as an X-Board). A connecting interface of the COF-type 1115S is arranged on one side of the driving circuit board 113a and 113b adjacent to the display area 1111, such as a mini LVDS interface or a P2P interface. Specifically, the driving circuit board 113a is provided with a display control circuit 1130, a connector CN1 and a connector CN3. The driving circuit board 113a is electrically connected to the display area 1111 through a plurality of source drivers, for example, seven COF-type source drivers 1115S. The driving circuit board 113b is provided with a connector CN4. The driving circuit board 113b is electrically connected to the display area 1111 through a plurality of source drivers, for example, five COF-type source drivers 1115S. The connector CN3 of the driving circuit board 113a is electrically connected with the connector CN4 of the driving circuit board 113b through a connecting member CL2. The connecting member CL2 is, for example, a flexible circuit board or a flexible flat cable (FFC).

The system board 13 includes a connector CN2 and a system-on-chip 131a.The connector CN2 of the system board 13 is connected with the connector CN1 of the driving circuit board 113a through the connecting member CL1. The connecting member CL1 is, for example, a single flexible flat cable (FFC), especially when the number of the driving circuit board in the source driving circuit board assembly is even. In this way, the system board 13 transmits control signals and all digital video image signals required by the active matrix panel (such as a liquid crystal panel) to the source driving circuit board assembly only through a single flexible flat cable (rather than through a plurality of flexible flat cables); the digital video image signals, for example, includes all RGB data required by the active matrix panel. It should be noted here that, a single flexible cable typically includes two connectors and a plurality of signal lines connected between the two connectors. In addition, it is worth mentioning that, the system board 13 of the embodiment is typically provided with a plurality of audio and video input interfaces, such as CVBS (Composite Video Broadcast Signal) interface, HDMI (High Definition Multimedia Interface) interface, etc.; the system board 13 is also called a main board, and is configured for decoding video image and audio signals inputted through the plurality of audio and video input interfaces, and then outputting the video image signal to the source driving circuit board assembly in digital signal format.

The system-on-chip 131a is configured for acquiring a type identification signal transmitted by the connecting member CL1 and identifying a corresponding P2P interface type according to the type identification signal; and transmitting corresponding P2P data according to the P2P interface type. Specifically, P2P interface types is one selected from a group consisting of an Integrated-Stream Protocol (iSP) interface, an Unified Standard Interface for TV (USI-T), a China BOE Point-to-Point Interface (CHPI), a China Star Point-to-Point Interface (CSPI), a Clock Embedded Point-to-Point Interface (CMPI) and a Clock Embedded Differential Signal (CEDS) interface. The above interface types are only common centralized P2P interface protocols. Different panel manufacturers also have their own P2P protocol(s). The P2P interface types of the disclosure are not limited to the above types, as long as the protocols designed by P2P mode can be implemented through the disclosure.

Additionally, the P2P interface further includes a pair of pins for clock training between the TX and the RX beside 12 pairs of P2P data interface pins. For different P2P protocols, the pin number and pin definition of clock training pins are different. The pin number of clock training pins is usually one or two. For example, ISP interface is configured for transmitting lock signal, and USI-T interface includes a SFC pin and a SRF pin. Of course, the specific pin number of the P2P interface depends on the type of signal.

In an embodiment of the disclosure, the acquiring a type identification signal and identifying a P2P interface type according to the type identification signal,, includes: acquiring a direct current (DC) voltage level data transmitted by a predetermined pin;

comparing the DC voltage level data with a preset value stored in advance to identify the P2P interface type corresponding to the DC voltage level data;

The pin number of preset pins in the embodiment is set according to the actual situation. If the pin number of the preset pins is one, there are at most two P2P types to be selected; if it is two, there are at most four P2P types to be selected; if it is three, there are at most eight P2P types to be selected, and so on; please refer to table 5, FIG. 2, and 3, two pins P2P_SEL1 and P2P_Sel2 are taken as an example for illustration, and the boot logic is that, after booting (or power on), the system board firstly reads HL setting of P2P_SEL1 and P2P_SEL2, identifies the correct P2P type, judges the definition of the P2P interface at the same time, selects the corresponding training mode in SOC to make clock training action between the TX and the Rx. After the training is successful, the display panel will start normally.

In this embodiment, the DC voltage level data are permutation and combination of the voltage levels transmitted by the added pins. If it includes one pin, there are two modes, H and L; if it includes two pins, there are four modes, LL, LH, HL, HH; if it includes three pins, there are eight modes, LLL, LLH, ......, HHL, HHH, and so on.

Please refer to FIG. 2 and 3, for example, if the pre-stored setting values are that: LL corresponding to SFC/SRF, LH corresponding to CRD, HL corresponding to BCC, and HH corresponding to lock. After reading the data of P2P_SEL1, P2P_SEL2, the system board judges the P2P type according to the above rules, and the corresponding training mode is selected in SOC, and make the clock training between the TX and the Rx. After the training is successful, the display panel will start normally.

In this embodiment, two pins are added to the 60-pin connectors of the system board and XB, one of which is used to transmit P2P selection clock signal (SEL_CLK) for defining clock period; the other one of which is used to transmit P2P selection data signal (SEL_DO) for transmitting high and low voltage levels. As a P2P type selection module, the added two pins can arranged to the original empty pins in 60-pin connector without increasing the total pin number of 60-pin connector. The system board judges the P2P type by reading the number of the high and low voltage levels, and makes a corresponding clock training action.

Please refer to FIG. 4 and 5. After booting (or power on), the system board uses the SEL_CLK as a clock signal, identifies times of occurrence of high or low voltage level transmitted by SEL_DO pin, judges the P2P type, and makes a corresponding clock training action. After the training is successful, the display panel will start normally. For example, if the times of occurrence of the high or low voltage level is 1, the P2P type will be judged as P2P MODE1; if the times of occurrence of the high or low voltage level is 2, the P2P type will be judged as P2P MODE2; if the times of occurrence of the high or low voltage level is 3, the P2P type will be judged as P2P Mode3, and so on.

In this embodiment, one pin is added to the 60-pin connectors of the system board and the XB board as the P2P selection data signal (P2P_SEL) for transmitting high and low voltage levels. The system board calculates a ratio between a high voltage level and a low voltage level, or counts the high and low voltage levels through the internal clock of SOC, judges the P2P type and make a corresponding clock training action.

Please refer to FIG. 7 and 8. After booting, the system board identifies and calculates the ratio of high level to high level transmitted by P2P_SEL pin, judges the P2P type, and makes a correct clock training action. After the training is successful, the display panel will start normally.

Please refer to FIG. 10 and 11, if the P2P type identification signal is stored in a FLASH MEMORY of the XB board, the SPI pins transmit the P2P type identification signal to the system board. Therefore, it is necessary to add 4-bit data in the SPI signal in advance as the P2P identification. After booting and receiving the data stored in a FLASH memory transmitted by SPI_DO, the system board firstly reads the P2P type identification signal, judges the P2P type, and makes a correct training action. After the training is successful, the data will be transmitted in a correct P2P data format, and the display panel will start normally.

Or, please refer to FIG. 12 and 13, if the P2P type identification signal is stored in an EEPROM of the XB board, 4-bit data is added to the IIC signal as the P2P identification in advance. After booting, receiving the data stored in the EEPROM transmitted by IIC_SDA, the system board firstly reads the P2P type identification signal, judges the P2P type, and makes a correct training action. After the training is successful, the data will be transmitted in a correct P2P data format, and the display panel will start normally.

Of course, the P2P type corresponding to the 4-bit data above-mentioned can be set in advance according to the actual situation, as long as it is consistent with the judgment conditions in the system board. In addition, it is not limited to 4-bit data and can be determined according to the number of P2P types.

ST-100SW single head lcd repair bonding machine is our best seller from 2018 till now. We have sold this bonding machine over 50 countries around the world.

Our bonding machine can repair all brands of TV screen panels up to 100 inches. It is a professional TV led lcd screen panel repairing machine and now the cof bonding machine is widely used by more and more TV repair shop and TV repair technician.

COF Bonding machine is a good device in TV screen panel repairing industry. It is used for repairing cof problems. Through bonding cof with TV glass panel side and pcb board, it can fix all the problems caused by TAB COF. More and more TV repair shops realize the bonding machine is a very helpful machine and can bring you good business.

Our cof bonding machine ST-100SW has 2 big screens which can show the cof lines clearly. It makes TV panel repairing easier and more precision. The bonding machine can repair TV screen panel size up to 100 inches with an extendable glass platform.

Accessories for bonding are included and sent with the machine. You only need to buy COF TAB IC. You can buy all the bonding machine accessories from us too.

After you purchase our bonding machine, welcome to visit our factory to learn how to use the bonding machine. We can also show you how to use the bonding machine to make sure you can use the cof machine successfully. At the same time, we have sold our bonding machine around the world, our customers will also be your good tutors on how to use the bonding machine.

our ST-100SW is a single head bonding machine. we have 4 sizes of the bonding head for your choice which are 68*1.4,68*1.2, 50*1.4 and 50*1.2. The single bonding head can both be used to bond COF with glass panel side and bond COF side with PCB board side.

(4) Usage: This product is used in a variety of FPC, COF, TAB and LCD Panel and PCB bonding. The bonding equipment can repair various screen display problems in a variety of sizes LCD vertical, horizontal, vertical band, horizontal belt, black belt, black, colored thread, ribbon , multi-line, black, black and white, vertical half display,horizontal half breakdown maintenance.

TAB bonding machine, also name COF bonding machine, ACF bonding machine, OLB Bonding machine, Chip on Film bonding machine. COF(Chip on Film, Chip on Flex).COF bonding machine is widely used in the TV/laptop/pad panel, it is very popular in the TV/laptop repairing for the LCD/LED/OLED panel bonding. For TV or laptop panel repairing COF bonding machine, has COF on glass bonding and COF on PCB board bonding. The COF Bonding machine also can do COF on flex cable, COF on film bonding, and maybe IC on film bonding. Normal theCOF bonding machine is Pulse heating bonding machine with Titanium alloy press bonding head.

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TAB bonding machine is a widely used machine all over the world. This bonding machine is based on the recent innovations as well as planned to repair the arrangements of LCD, LED, and television. This bonding machine may consist of has two Digital Microscope, and also has a Digital Pressure Gauge. The ACF bonding machine consists of vacuum generator which may help to hold the panel during the bonding process. It may also provide the quick as well as easy solutions for various mobile problems. COF (TAB Bonding Machine) is fast as well as it is very easy to access this bonding machine. This bonding machine is able to provide high accuracy repair apparatus for repair different size of the LED or LCD screen as well as LCD Panel. COF bonding machine also consists a process of repairing the technical equipment in an easy way.

We provide the various sizes and types of this machine, as well as all the services, are available if any defect may occur in the machine. Anisotropic conductive film (ACF) bonding machine commonly use in connectivity with electrical and mechanical connections from electronics driver to glass substrate of the LCD/LED/TV. During the ACF bonding process, heat and pressure are applied via a thermode (or hot bar) on to the ACF film or other component that is sandwiching the ACF film.

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This article from semiconductor firm, MagnaChip covers the role that DDIC (display driver IC) technology plays in the function of modern display technology – and ultimately considers the impact it will have on the next generation of OLED (organic light emitting diode) screens in mobile devices.

Flat panel display technology is divided into two types: non-emissive display, which requires an external light source; and emissive display, which produces its own light organically. Thin-film transistor (TFT) LCD is a non-emissive and older display technology which requires an external light source to work, while OLED (organic light emitting diode) is considered an emissive display technology that does not require a backlight, because each pixel provides its own illumination.

An OLED display driver integrated circuit (DDIC) is a component that controls the OLED display panel: it enables thinner and bezel-less displays that are also more flexible and foldable and provide a wide range of colours that are true to the content being displayed. OLED also requires less power consumption than LCD, which causes less drain on the battery and extends the useful operating time of a device.

A DDIC sends a driving signal and the required data to the display panel in a form of electrical signals, to represent image signals such as letters and images. The DDIC resides in the OLED panel and differs between PM OLED and AM OLED panels. In the case of the former, by supplying a current into both vertical and horizontal panel ends, the pixels will emit light where the currents cross; therefore, by controlling the amount of crossing current, the intensity of light is also controlled.

As for AM OLED, moreover, each pixel in the panel has a TFT (thin film transistor) and data storage capacitor, which is capable of controlling the brightness of each pixel in ‘degrees of gray’, which leads to lower power consumption and a longer panel lifetime. When the DDIC commands all of the AM OLED’s pixels, each is controlled through TFT. Display pixels consist of subpixels that represent RGB. With such sub-pixels being controlled by the TFT, and given that the DDIC sends signals to the TFT, it is the DDIC that ultimately controls the pixels directly. Consider, therefore, the TFT functioning as a switch that drives RGB sub-pixels – while the DDIC functions as a type of ‘traffic light’ to instruct such a switch on how to operate.

To realise such flexible displays, DDIC COF (chip on film) technology is a requirement. COG (chip on glass) is a method of directly mounting the DDIC onto a rigid glass substrate, whereas COF, and also COP (chip on plastic), sees the DDIC being directly bonded onto the flexible substrate – to ensure the realisation of flexible displays.

To specify, COF is a packaging method of attaching DDIC to a panel substrate by bonding thin film, whereas COP is a method of mounting DDIC directly onto the substrate. The flexible qualities of the former make it possible to design the side area of a screen (often called the bezel), to be narrower than COG. This results in a relatively larger screen-to-body ratio. In other words, it can create a ‘bezel-less’ (or full screen) display. Moreover, in order to realise flexible displays where the screen itself bends, the DDIC package must also be flexible; and this is why it is imperative to apply COF technology. By contrast, LCD drivers can not physically fold or bend.

With the increasing resolution of smartphone displays, the number of DDIC channels connected to an individual pixel of the display panel also increases. In order to support high resolution, a ‘double-sided 2 Metal COF’ package technology is required. In general, while the resolution of FHD (full high definition) and below can be achieved by 1-layer metal COF, but resolution of QHD (quad high definition) and above – with a 30 percent increase in the number of channels, requires 2 metal COF. Therefore, for these high resolution formats, it is essential that ‘fine-circuit’ technology be embedded on both sides of the COF package for DDIC.

While smartphone display resolution has continued to improve, the downside is that this leads to more power consumption, therefore reducing the battery life of mobile devices. Also, when it comes to the RAM (random access memory) for storing display pattern data within a DDIC, a higher resolution increases the amount of display pattern data stored in the RAM. RAM capacity must therefore increase accordingly, which also increases the chip size of the DDIC.

The present disclosure relates to the technical field of displays, and in particular, to an active-matrix organic light-emitting diode (AMOLED) display panel and a corresponding display device. BACKGROUND OF INVENTION

With development of display industry technologies, requirements of customers for display panels are increasingly high. For example, for some high-end display panels, customers require that a narrow bezel is designed. The current active-matrix organic light-emitting diode (AMOLED) display panel includes a display area C1 configured to set a pixel structure, a binding area C2 configured to place a chip on film (COF) or a chip binding area configured to place a chip on plastic (COP), a fan-out area C3 connected to “Data” signals in a pixel circuit of the display area C1 and a bending area C4 for bending. The binding area is bent to a location below the panel by bending the bending area C4, and a lower bezel of original rigid display panel may be diminished, as shown FIG. 1.

In the current design, a value of a distance D from the display area C1 to the bending area C4 is still relatively large. A main reason is that a wiring space of the fan-out area C3 requires to be considered, and a height required for the current fan-out area C3 is mainly affected by factors, such as a quantity of fan-out wires. That is, when the quantity of wires is relatively small, the height required for the fan-out area C3 may be reduced.

In the current AMOLED display panel, “Pentile” pixel arrangement is used. As shown in FIG. 2, a structure of the pixel arrangement includes a pixel 1 obtained by combining two sub-pixels, namely, a red sub-pixel and a green sub-pixel, and a pixel 2 obtained by combining two sub-pixels, namely, a blue sub-pixel and a green sub-pixel. The two pixels share neighboring sub-pixels and form repeating units arranged in an array manner. The repeating units are arranged along a row direction. Moreover, a direction of a short side of each sub-pixel is consistent with the row direction, and a direction of a long side of each sub-pixel is consistent with a column direction, such that each pixel requires two “Data” signal lines (data line) and one “Scan” signal line (gate line), so as to increase the quantity of fan-out wires and increase the height required for the fan-out area. SUMMARY OF INVENTION

Embodiments of the present disclosure provide an active-matrix organic light-emitting diode (AMOLED) display panel and a corresponding display device, in which a quantity of data lines is reduced. That is to reduce a quantity of fan-out wires and reduce a height of a fan-out area, to resolve a technical problem that a “Pentile” pixel arrangement design is used in the current AMOLED display panel and each pixel requires two data lines, causing an increase in the quantity of fan-out wires and an increase in the height required for the fan-out area.

An embodiment of the present disclosure provides an AMOLED display panel, which includes a plurality of first pixel units and a plurality of second pixel units, wherein the first pixel units and the second pixel units are alternately disposed along a horizontal direction and along a vertical direction to form a pixel structure arranged in a matrix manner;

wherein the first pixel unit includes a first sub-pixel and a second sub-pixel disposed side by side with the first sub-pixel; wherein the second pixel unit includes another first sub-pixel and a third sub-pixel disposed side by side with the another first sub-pixel; wherein the first pixel unit and the third sub-pixel adjacent to the second pixel unit constitute a pixel point, and the second pixel unit and a second sub-pixel adjacent to the first pixel unit constitute a pixel point;

wherein in the first pixel unit, the first sub-pixel and the second sub-pixel are arranged along a direction in which the data lines extend, and the first sub-pixel and the second sub-pixel share one of the data lines; wherein in the second pixel unit, the first sub-pixel and the third sub-pixel are arranged along the direction in which the data lines extend, and the first sub-pixel and the third sub-pixel share one of the data lines;

wherein the first sub-pixel, the second sub-pixel, and the third sub-pixel are rectangular and have areas in equal, and a direction extending along a long side of each of the first sub-pixel, the second sub-pixel, and the third sub-pixel is perpendicular to the direction in which the data lines extend; and

In the AMOLED display panel of the present disclosure, the pixel circuit is a 7T1C pixel circuit, and the 7T1C pixel circuit includes a driving transistor configured to determine driving current of a driving circuit,

In the AMOLED display panel of the present disclosure, the 7T1C pixel circuit includes a capacitor for voltage compensation, the capacitor includes a straight-strip-shaped lower electrode plate and a straight-strip-shaped upper electrode plate located over the straight-strip-shaped lower electrode plate, and the first gate is a portion of the straight-strip-shaped lower electrode plate.

In the AMOLED display panel of the present disclosure, the pixel circuit is a 7T1C pixel circuit, and the 7T1C pixel circuit includes a transistor configured to control a reference signal VI transmitted to a control end of the driving transistor;

An embodiment of the present disclosure provides another AMOLED display panel, which includes a plurality of first pixel units and a plurality of second pixel units, wherein the first pixel units and the second pixel units are alternately disposed along a horizontal direction and along a vertical direction to form a pixel structure arranged in a matrix manner;

wherein the first pixel unit includes a first sub-pixel and a second sub-pixel disposed side by side with the first sub-pixel; wherein the second pixel unit includes another first sub-pixel and a third sub-pixel disposed side by side with the another first sub-pixel; wherein the first pixel unit and the third sub-pixel adjacent to the second pixel unit constitute a pixel point, and the second pixel unit and a second sub-pixel adjacent to the first pixel unit constitute a pixel point;

wherein the pixel structure further includes a plurality of data lines connected to the sub-pixels; wherein in the first pixel unit, the first sub-pixel and the second sub-pixel are arranged along a direction in which the data lines extend, and the first sub-pixel and the second sub-pixel share one of the data lines; and wherein in the second pixel unit, the first sub-pixel and the third sub-pixel are arranged along the direction in which the data lines extend, and the first sub-pixel and the third sub-pixel share one of the data lines.

In the another AMOLED display panel of the present disclosure, the first sub-pixel, the second sub-pixel, and the third sub-pixel are rectangular and have areas in equal, and a direction extending along a long side of each of the first sub-pixel, the second sub-pixel, and the third sub-pixel is perpendicular to the direction in which the data lines extend.

In the another AMOLED display panel of the present disclosure, the pixel structure includes a pixel circuit configured to drive any one of the first sub-pixel, the second sub-pixel, and the third sub-pixel to emit light, and the pixel circuit is one of 7T1C, 6T1C, 6T2C, 5T1C, and 4T1C.

In the another AMOLED display panel of the present disclosure, the pixel circuit is a 7T1C pixel circuit, and the 7T1C pixel circuit includes a driving transistor configured to determine driving current of a driving circuit;

In the another AMOLED display panel of the present disclosure, the 7T1C pixel circuit includes a capacitor for voltage compensation, the capacitor includes a straight-strip-shaped lower electrode plate and a straight-strip-shaped upper electrode plate located over the straight-strip-shaped lower electrode plate, and the first gate is a portion of the straight-strip-shaped lower electrode plate.

In the another AMOLED display panel of the present disclosure, the pixel circuit is a 7T1C pixel circuit, and the 7T1C pixel circuit includes a transistor configured to control a reference signal VI transmitted to a control end of the driving transistor;

In the another AMOLED display panel of the present disclosure, the first sub-pixel is a green sub-pixel, the second sub-pixel is a blue sub-pixel, and the third sub-pixel is a red sub-pixel.

The present disclosure further relates to a display device including an AMOLED display panel, which includes a plurality of first pixel units and a plurality of second pixel units, wherein the first pixel units and the second pixel units are alternately disposed along a horizontal direction and along a vertical direction to form a pixel structure arranged in a matrix manner;

wherein the first pixel unit includes a first sub-pixel and a second sub-pixel disposed side by side with the first sub-pixel; wherein the second pixel unit includes another first sub-pixel and a third sub-pixel disposed side by side with the another first sub-pixel; wherein the first pixel unit and the third sub-pixel adjacent to the second pixel unit constitute a pixel point, and the second pixel unit and a second sub-pixel adjacent to the first pixel unit constitute a pixel point; and

wherein the pixel structure further includes a plurality of data lines connected to the sub-pixels. In the first pixel unit, the first sub-pixel and the second sub-pixel are arranged along a direction in which the data lines extend, and the first sub-pixel and the second sub-pixel share one of the data lines, and in the second pixel unit, the first sub-pixel and the third sub-pixel are arranged along the direction in which the data lines extend, and the first sub-pixel and the third sub-pixel share one of the data lines.

In the display device of the present disclosure, the first sub-pixel, the second sub-pixel, and the third sub-pixel are rectangular and have areas in equal. An extending direction of a long side of each of the first sub-pixel, the second sub-pixel and the third sub-pixel is perpendicular to the extending direction of the data lines.

Compared with AMOLED display panels in the prior art, the AMOLED display panel and the corresponding display device of the present disclosure are implemented by the first sub-pixel and the second sub-pixel in the first pixel unit share one of the data lines, and the first sub-pixel and the third sub-pixel in the second pixel unit share one of the data lines, such that a quantity of data lines is reduced, thereby reducing a quantity of fan-out wires, and reducing a space required by wiring in a fan-out area, so as to reduce a size of a lower bezel.

Additionally, when the 7T1C pixel circuit is configured to drive the sub-pixel, the channel area of the driving transistor is linear, thereby reducing a process difficulty. The first channel area and the second channel area of the transistor configured to control the reference signal VI transmitted to a control end of the driving transistor are oblique-line-shaped, thereby increasing an effective length of the channel area and reducing a leakage current. It resolves a technical problem that a “Pentile” pixel arrangement design used in the current AMOLED display panel, in which each pixel requires two data lines, that causes an increase in the quantity of fan-out wires and increases an height required for the fan-out area. BRIEF DESCRIPTION OF DRAWINGS

FIG. 5 is a schematic diagram of a structure of a 7T1C circuit of a first pixel unit of an embodiment of an AMOLED display panel according to the present disclosure (circuit structures of the first pixel unit and the second pixel unit are the same);

With reference to figures in the accompanying drawings, a same component symbol represents a same component. The following description is based on exemplified specific embodiments of the present disclosure, and the embodiments should not be considered to limit other specific embodiments of the present disclosure that are not detailed herein.

Referring to FIG. 3, which is a schematic diagram of arrangement of a pixel structure of an embodiment of an active-matrix organic light-emitting diode (AMOLED) display panel according to the present disclosure.

The AMOLED display panel of the present embodiment includes a plurality of first pixel units 10 and a plurality of second pixel units 20. The first pixel units 10 and the second pixel units 20 are alternately disposed along a horizontal direction and along a vertical direction to form a pixel structure arranged in a matrix manner.

The first pixel unit a includes a first sub-pixel 11 and a second sub-pixel 12 disposed side by side with the first sub-pixel 11. The second pixel unit b includes another first sub-pixel 11 and a third sub-pixel 13 disposed side by side with the another first sub-pixel 11. The first pixel unit a and a third sub-pixel 13 adjacent to the second pixel unit b constitute a pixel point. The second pixel unit b and a second sub-pixel 12 adjacent to the first pixel unit a constitute a pixel point.

The pixel structure further includes a plurality of data lines Data connected to sub-pixels. In the first pixel unit a, the first sub-pixel 11 and the second sub-pixel 12 are arranged along a direction in which the data lines Data extend. The first sub-pixel 11 and the second sub-pixel 12 share one of the data lines Data. In the second pixel unit b, the first sub-pixel 11 and the third sub-pixel 13 are arranged along the direction in which the data lines Data extend. The first sub-pixel 11 and the third sub-pixel 13 share one of data lines Data.

A sub-pixel includes a light-emitting device unit and a corresponding pixel driving circuit unit. In the present embodiment, a disposition of side by side between sub-pixels is essentially a disposition of side by side between pixel driving circuit units.

Compared with the prior art in which two sub-pixels, namely, a red sub-pixel and a green sub-pixel in a pixel 1 (as shown in FIGS. 2 and 6) are arranged along a direction that a gate line (Scan) extends, such that each of the red and green sub-pixels requires one of data lines Data, and shares the gate line (Scan), additionally, the sub-pixels are longitudinally arranged as a whole. The AMOLED display panel of the present embodiment is achieved by the first sub-pixel 11 and the second sub-pixel 12 in the first pixel unit a share one of the data lines Data, and by the first sub-pixel 11 and the third sub-pixel 13 in the second pixel unit b share one of the data lines Data, such that a quantity of the data lines Data is reduced, thereby reducing a quantity of fan-out wires, and reducing a space required for wiring in a fan-out area, so as to reduce a size of a lower bezel.

Compared with the AMOLED display panel in the prior art, although such disposition of the present embodiment increases a quantity of gate lines, the quantity of data lines Data is reduced by one half, thereby reducing a space required for wiring in a fan-out area, so as to reduce a size of a lower bezel. On the other band, the quantity of gate lines Scan is increased, but if the present disclosure and the prior art use the same driving manner, widths of left and right bezels are increased. Therefore, interlace driving or multi-stage driving may be for gate driver on array (GOA) circuits of two side areas to reduce the widths of the left and right bezels.

The first sub-pixel 11, the second sub-pixel 12 and the third sub-pixel 13 are rectangular and have areas in equal. A direction extending along a long side of each of the first sub-pixel 11, the second sub-pixel 12, and the third sub-pixel 13 is perpendicular to the direction in which the data lines Data extend. In such disposition, the entire structure of the sub-pixel horizontally extend, thereby facilitating the fabrication of a driving transistor in a driving circuit.

The driving transistor T1 is configured to determine driving current of the pixel driving circuit. The light-emitting device OLED is configured to illuminate to display in response to the driving current. The second transistor T2 is configured to control transmission of a data signal Data. The third transistor T3 is configured to control on and off of a control end and a second end of the driving transistor T1. The fourth transistor T4 is configured to control a reference signal VI transmitted to the control end of the driving transistor T1. The fifth transistor T5 is configured to control a first power signal VDD transmitted to a first end of the driving transistor T1. The sixth transistor T6 is configured to transmit the driving current from the driving transistor T1 to the light-emitting device OLED.

A control end of the fourth transistor T4 is connected to the gate driving signal Scan(n), a first end of the fourth transistor T4 is connected to the reference signal VI, a second end of the fourth transistor T4 is connected to a first end of the third transistor T3, a second end of the capacitor C1, and the control end of the driving transistor T1. The control end of the driving transistor T1 is connected to the second end of the capacitor C1, the second end of the fourth transistor T4 and the first end of the third transistor T3. The first end of the driving transistor T1 is connected to a second end of the second transistor T2 and a first end of the fifth transistor T5. The second end of the driving transistor T1 is connected to a second end of the third transistor T3 and a first end of the sixth transistor T6. A control end of the second transistor T2 is connected to a driving signal Scan(n), and a first end of the second transistor T2 is connected to a data signal Data. A control end of the fifth transistor T5 is connected to a driving signal EM(n). A second end of the fifth transistor is connected to a first end of the capacitor C1 and the first power signal VDD. An anode of the light-emitting device OLED is connected to a second end of the sixth transistor T6. A cathode of the light-emitting device OLED is connected to a second power signal VSS.

Compared with a width of a U-shaped channel area of a driving transistor T1′ (as shown in FIG. 6) in a 7T1C circuit structure of a pixel unit of the AMOLED display panel in the prior art, the linear channel area enables a channel width to be more easily controlled, and surface uniformity is better. Because the U-shaped channel has corners, which is more difficult to control a channel width at the corners in a manufacturing process.

The present disclosure further relates to a display device including an AMOLED display panel, which includes a plurality of first pixel units and a plurality of second pixel units. The first pixel units and the second pixel units are alternately disposed along a horizontal direction and along a vertical direction to form a pixel structure arranged in a matrix manner.

The first pixel unit includes a first sub-pixel and a second sub-pixel disposed side by side with the first sub-pixel. The second pixel unit includes another first sub-pixel and a third sub-pixel disposed side by side with the another first sub-pixel. The first pixel unit and a third sub-pixel adjacent to the second pixel unit constitute a pixel point. The second pixel unit and a second sub-pixel adjacent to the first pixel unit constitute a pixel point.

The pixel structure further includes a plurality of data lines connected to sub-pixels. In the first pixel unit, the first sub-pixel and the second sub-pixel are arranged along a direction in which the data lines extend, and the first sub-pixel and the second sub-pixel share one of the data lines, and in the second pixel unit, the first sub-pixel and the third sub-pixel are arranged along the direction in which the data lines extend, and the first sub-pixel and the third sub-pixel share one of the data lines.

In the display device of the present disclosure, the first sub-pixel, the second sub-pixel, and the third sub-pixel are rectangular and have areas in equal. An extending direction of a long side of each of the first sub-pixel, the second sub-pixel and the third sub-pixel is perpendicular to the extending direction of the data lines.

Compared with AMOLED display panels in the prior art, the AMOLED display panel and the corresponding display device of the present disclosure are implemented by the first sub-pixel and the second sub-pixel in the first pixel unit share one of the data lines, and the first sub-pixel and the third sub-pixel in the second pixel unit share one of the data lines, such that a quantity of data lines is reduced, thereby reducing a quantity of fan-out wires, and reducing a space required by wiring in a fan-out area, so as to reduce a size of a lower bezel.

Additionally, when the 7T1C pixel circuit is configured to drive the sub-pixel, the channel area of the driving transistor is linear, thereby reducing a process difficulty. The first channel area and the second channel area of the transistor configured to control the reference signal VI transmitted to a control end of the driving transistor are oblique-line-shaped, thereby increasing an effective length of the channel area and reducing a leakage current. It resolves a technical problem that a “Pentile” pixel arrangement design used in the current AMOLED display panel, in which each pixel requires two data lines, that causes an increase in the quantity of fan-out wires and increases a height required for the fan-out area.