terasic multi touch lcd module manufacturer

The Terasic Multi-touch LCD Module (MTL) is an all-purpose capacitive touch-screen for FPGA applications and provides multi-touch gesture and single-touch support. An IDE cable with an IDE to GPIO adapter (ITG) is used to interface with various Terasic FPGA development boards through a 2x20 GPIO interface on the MTL.

The kit provides everything you need to develop multimedia applications using a digital multi-touch panel and includes complete reference designs and source code for implementing a photo viewer demonstration and a color painter.

I am having difficulties getting the MTL Paint Demo to work under Quartus 15.0. When building the BSP, the ALT_ENHANCED_INTERRUPT_API_PRESENT flag is set. I make the appropriate modifications to the MTC_Init and mtc_ISR routines to handle the newer rather than the legacy interrupt interface and I can receive interrupts. I have a problem writing to the LCD, either through the gui_vpg or gui calls. If I choose the gui_vpg option and step through, the call to never returns. It ultimately calls vid_paint_block. It appears that this routine hangs after processing 128 lines when attempting the memcpy near the end of that routine.

offers expertise in FPGA/ASIC design, high speed board design and layout, low cost board design, device drivers, and all other supporting software and documentation. They are dedicated to providing a wide range of various FPGA based boards for academia and industries. Terasic"s cutting-edge design and manufacturing capabilities provide state of the art products and exceptional services to their customers. Terasic products have enjoyed phenomenal success all over the world and continues to set the standard in development hardware.

This project describes how to use the Linux BSP (Board Support Package) provide by Terasic. Users can develop touch-screen GUI program easily with the BPS even without support from Linux X Window.

Figure 1 shows the block diagram of Linux BSP for Atlas-SoC kit with Terasic Multi-Touch LCD Module Second Edition(MTL2) . The BPS incudes two major parts:

The Linux image files are implemented on HPS/ARM and the Quartus project is implemented on FPGA/Qsys. The Linux image files include the pre-built Linux system. Users can create a Linux bootable microSD card with the image files. The Quartus project includes the controller for VGA display and the touch-screen controller for touch-screen panel. For how to create a Linux bootable microSD card with the image files, please refter to chapter 5 of the DE0-Nano-SoC_Getting_Started_Guide.pdf. Note that, please setting the MSEL switch to "0000".

The VGA display part is designed to display the Linux console or desktop on the LCD touch panel. Altera Video and Image Processing (VIP) suite is used to implement this function. The Linux frame buffer driver fills up the DDR3 with data to be displayed, and the VIP frame-reader component reads the data from the DDR3 in a DMA manner. The video data is streamed into the VIP Clocked Video Output component. Finally, the VIP Clocked Video Output component drives the VGA DAC chip to display the video data.

A customized component developed by Terasic in Qsys is used to communicate with the touch-screen panel. The component interfaces with the touch-screen panel through I2C -like protocol, and reports the status of touch-screen panel through a parallel bus.

The DE1-SoC-MTL2 Development Kit is a comprehensive design environment with everything embedded developers need to create processing-based systems. The DE1-SoC-MTL2 delivers an integrated platform including hardware, design tools, and reference designs for developing embedded software and hardware platforms in a wide range of applications. The fully integrated kit allows developers to rapidly customize their processor and IP to best suit their specific application. The DE1-SoC-MTL2 features a DE1-SoC development board targeting Altera Cyclone® V SX SoC FPGA, as well as a capacitive LCD multimedia color touch panel which natively supports five points multi-touch and gestures.

The all-in-one embedded solution offered on the DE1-SoC-MTL2, in combination of a LCD touch panel and digital image module, provide s embedded developers the ideal platform for multimedia applications with unparallel processing performance. Developers can benefit from the use of FPGA-based embedded processing system such as mitigat ing design risk and obsolescence, design reuse, lowering bill of material (BOM) costs by integrating powerful graphics engines within the FPGA.

1.1 About the Package ......................................................................................................................................3 1.2 Power Adapter for MTL .............................................................................................................................4 1.3 Setup License for Terasic Multi-touch IP ...................................................................................................5 1.4 Assembly ....................................................................................................................................................6 1.5 Connectivity ...............................................................................................................................................7 1.6 Getting Help ...............................................................................................................................................7CHAPTER 2

2.1 Features ......................................................................................................................................................8 2.2 MTL Kit......................................................................................................................................................8 2.3 Multi-touch LCD Module (MTL)...............................................................................................................8 2.4 IDE Cable ................................................................................................................................................. 11 2.5 ITG Adapter.............................................................................................................................................. 11CHAPTER 3

3.1 Pin Definition of 2x20 GPIO Connector ..................................................................................................13 3.2 Using LCD................................................................................................................................................15 3.3 Using Terasic Multi-touch IP....................................................................................................................15CHAPTER 4

4.1 Operation Description ..............................................................................................................................18 4.2 Block Diagram of the ePhoto Design .......................................................................................................19 4.3 Loading Photos into FLASH ....................................................................................................................20 4.4 Demonstration for Terasic DE2-115 FPGA Board ...................................................................................21 4.5 Custom Display Photo..............................................................................................................................23

5.1 Operation Description ..............................................................................................................................24 5.2 System Description...................................................................................................................................25 5.3 Demonstration for Terasic DE2-115 FPGA Board ...................................................................................26 5.4 Demonstration Source Code.....................................................................................................................27CHAPTER 6

IntroductionThe Terasic Multi-touch LCD Module (MTL) is an all-purpose capacitive touch-screen for FPGA applications and provides multi-touch gesture and single-touch support. An IDE cable with an IDE to GPIO (ITG) adapter is used to interface with various Terasic FPGA development boards through a 2x20 GPIO interface on the MTL. The kit contains complete reference designs and source code for an ePhoto demonstration and Painter application. This chapter provides the key information about the kit.

1.1 About the PackageThe MTL kit comes with the following contents: Multi-touch LCD Module IDE Cable with ITG Adapter MTL System CD-ROM 5V Power Supply Four Silicon Footstands

1.2 Power Adapter for MTLFigure 1-2 shows the power adapter for the MTL. Due to the fact that the LCD panel in the MTL consumes more power than some boards can provide a dedicated power adapter for MTL is required. Note: the power adapter is not necessary for the DE2-115 FPGA board.

1.3 Setup License for Terasic Multi-touch IPTo utilize the multi-touch panel in a Quartus II project, a Terasic Multi-Touch IP is required. After a license file for Quartus II is installed, there is one more license file needed to implement Terasics Multi-touch IP. Error messages will be displayed if the license file is not added before compiling projects using Terasic Multi-touch IP. The license file is located at: MTL System CD\License\license_multi_touch.dat There are two ways to install the License. The first one is to add the license file (license_multi_touch.dat) to the licensed file listed in Quartus II, as shown in Figure 1-3.

The second way is to add license content to the existing license file. The procedures are listed below: Use Notepad or other text editing software to open the file license_multi_touch.dat. 1. The license contains the FEATURE lines required to license the IP Cores as shown in Figure 1-4.

Open your Quartus II license.dat file in a text editor. Copy everything under license_multi_touch.dat and paste it at the end of your Quartus II license file. (Note: Do not delete any FEATURE lines from the Quartus II license file. Doing so will result in an unusable license file.) . Save the Quartus II license file.

1.6 Getting HelpHere is information of how to get help if you encounter any problem: Office Hours: 9:00 a.m. to 6:00 p.m. (GMT +8) Telephone: +886-3-550-8800 Email: support@terasic.com

2.1 FeaturesThe key features of this module are listed below: 800x480 pixel resolution LCD with 24-bit color depth Two-point multi-gesture support Single touch support IDE interface 2x20 GPIO interface with ITG adapter

2.4 IDE CableThe connection cable included is a standard IDE cable. However, to achieve the best performance, we strongly recommend users use the bundled IDE cable only. Third-party IDE cables may cause the MTL to malfunction, or even damage the module. The IDE cable is shown in Figure 2-5.

Using the MTLThis chapter provides information on how to control the Multi-touch LCD Module (MTL) hardware, including definition of 2x20 GPIO interface, LCD control, and multi-touch control signals.

3.1 Pin Definition of 2x20 GPIO ConnectorThe 2x20 GPIO female connector is designed to directly connect to the 2x20 GPIO male connector on the Terasic FPGA development boards. Figure 3-1 shows the signal names of the 2x20 GPIO from the ITG adapter.

MTL_DCLK Output Output MTL_R[0] Output MTL_R[1] Output MTL_R[2] Output MTL_R[3] Output MTL_R[4] Output MTL_R[5] Output MTL_R[6] Output MTL_R[7] Output MTL_G[0] Output MTL_G[1] Output MTL_G[2] Output MTL_G[3] Output MTL_G[4] Output MTL_G[5] Output MTL_G[6] Output MTL_B[0] MTL_G[7] Output Output MTL_B[1] Output MTL_B[2] Output MTL_B[3] Output MTL_B[4] Output MTL_B[5] Output MTL_B[6] Output MTL_B[7] MTL_HSD Output MTL_VSD Output MTL_TOUCH_I2C_SCL Output MTL_TOUCH_I2C_SDA Inout MTL_TOUCH_INT_n Input 14

3.2 Using LCDThe LCD features 800x480 pixel resolution, and runs a 33 MHz pixel rate. No configuration is required to drive the LCD. The timing specification is defined as in the Table 3-2. Table 3-2 LCD TimingItem Typical Value Unit

3.3 Using Terasic Multi-touch IPTerasic Multi-touch IP is provided for developers to retrieve user inputs, including multi-touch gestures and single-touch. The file name of this IP is i2c_touch_config and it is encrypted. To compile projects with the IP, users need to install the IP license first. For license installation, please refer to Chapter 1 in this document. The license file is located at: MTL System CD\License\license_multi_touch.dat The IP decodes I2C information and outputs coordinate and gesture information. The IP interface is shown below:

The signal purpose of the IP is described in Table 3-3. The IP requires a 50 MHz signal as a reference clock to the iCLK pin and system reset signal to iRSTN. iTRIG, I2C_SCLK, and IC2_SDAT pins should be connected of the MTL_TOUCH_INT_n, MTL_TOUCH_I2C_SCL, and MTL_TOUCH_I2C_DAT signals in the 2x20 GPIO header respectively. When oREADY rises, it means there is touch activity, and associated information is given in the oREG_X1, oREG_Y1, oREG_X2, oREG_Y2, oREG_TOUCH_COUNT, and oREG_GESTURE pins. For the control application, when touch activity occurs, it should check whether the value of oREG_GESTURE matched a pre-defined gesture ID defined in Table 3-3. If it is not a gesture, it means a single-touch has occurred and the relative X/Y coordinates can be derived from oREG_X1 and oREG_Y1. Table 3-3 Interface Definitions of Terasic Multi-touch IPPin Name Direction Description

Connect to 50MHz Clock Connect to system reset signal Connect to Interrupt Pin of Touch IC Rising Trigger when following six output data is valid 10-bits X coordinate of first touch point 9-bits Y coordinate of first touch point 10-bits X coordinate of second touch point 9-bits Y coordinate of second touch point 2-bits touch count. Valid value is 0, 1, or 2. 8-bits gesture ID (See Table 3-4) Connect to I2C Clock Pin of Touch IC Connect to I2C Data Pin of Touch IC

ePhoto DemonstrationThis chapter describes how to use MTL to design a simple photo viewer. The demonstration can support the following Terasic FPGA boards: DE2-115 DE2

4.1 Operation DescriptionThis demonstration implements a simple photo viewer. Before running this demonstration, three 800x480 photos should be vertically merged into one 800x1440 photo and be stored in FLASH of the FPGA board in advance. In this demonstration, users can browse each photo by using single touch west or east gesture to select the previous or next photo, as shown in Figure 4-1. .

4.2 Block Diagram of the ePhoto DesignThis section describes the block diagram of the ePhoto demonstration to give users a better understanding of the code provided. Figure 4-3 shows the block diagram of the ePhoto demonstration. When the demonstration starts up, the system will control the Flash Controller to read the RGB data of three photos stored in the FLASH, and write the data into SDRAM by using the writing port of the SDRAM. The SDRAM Controller provides two reading ports and two writing ports. In this demonstration, only one reading port and one write porting are used. To display the selected photo on the 800x480 LCD, the VGA Controller will retrieve the photo data via reading the port of the SDRAM, and drive the LCD display with the retrieved photo data. The VGA Controller retrieves the photo data at a rate of 60 photos per second. Zoom handles the photo zooming process. The displayed photo is zoomed before being sent to the LCD display. When users touch the MTL screen, I2C Touch Config will receive an interrupt signal from the touch screen. When an interrupt is detected, I2C Touch Config will read touch information from the touch panel and assert the oREADY signal. When Touch Controller detects a rising signal of oREADY, it will read touch information and determine the input, which may be a gesture or a single-point touch. If a west or east gesture is detected, it will change the reading port address of the desired active photo in the SDRAM Controller. If a zoom-in or zoom-out gesture is detected, it will change the zooming factor in Zoom. For multi-touch gesture processing, a Terasic Memory-Mapped IP I2C_Touch_Config is used to retrieve the touch information. For IP-usage details, please refer to the Chapter 3 in this document. Note: the IP is encrypted, so the license should be installed before compiling the Quartus II project.

4.4 Demonstration for Terasic DE2-115 FPGA BoardThis section shows how to setup the painter demo on the Terasic DE2-115 FPGA Board. For other Terasic FPGA boards, the setup procedures are similar.

Execute DemonstrationProcedure to execute demonstration: 1. 2. 3. 4. 5. 6. Make sure the DE2-115 is powered off. Mount the ITG adapter onto the 2x20 GPIO 0 expansion header of the DE2-115. Connect the DE2-115 USB-Blaster USB port to the PC USB Port with a USB Cable. Power on the DE2-115* FPGA Development Board. Make sure Quartus II 10.1 and NIOS II 10.1 are installed in your system. If you havent already, store pictures into the flash memory. For more detailed instructions please refer to section 4.3 Loading Photos into FLASH. 7. Copy the folder Demonstrations\RTL\DE2_115_EPHOTO\demo_batch in the MTL System CD onto your system and execute test.bat. 8. A photo should be displayed in the LCD, as shown in Figure 4-5. 9. Slide left or right with one finger on the touch panel to display the previous and next photos respectively. 10. Slide with two fingers in the opposite direction to zoom-in on the picture and pinch two fingers together to zoom the picture out.

Table 4-2 lists the demonstration bitstream files for various Terasic FPGA boards. Table 4-2 Bitstream Files for Various FPGA BoardsFPGA Board Quartus II Project Directory FPGA Bitstream Used

Painter DemonstrationThis chapter shows how to implement a painter demo on the Multi-Touch LCD Module based on SOPC Builder and the Alteras Video and Image Processing Suite (VIP). The design demonstrates how to use multi-touch gestures and single-touch. The demonstration requires the following hardware: Terasic FPGA Board Multi-touch LCD Module

5.2 System DescriptionFor LCD display processing, the reference design is developed based on Alteras Video and Image Processing Suite (VIP). The Frame Reader VIP is used for reading display content from the associated video memory, and VIP Video Out is used to display the display content. The display content is drawn by the NIOS II processor according to user input.

For multi-touch processing, a Terasic Memory-Mapped IP is used to retrieve the user input, including multi-touch gestures and single-touch coordinates. For IP--usage details please refer to the Chapter Three in this document. Note: the IP is encrypted, so the license should be installed before compiling the Quartus II project. Figure 5-5 shows the system generic block diagram of demonstration reference design.

5.3 Demonstration for Terasic DE2-115 FPGA BoardThis section shows how to setup the painter demo on the Terasic DE2-115 FPGA Board. For other Terasic FPGA boards, the setup procedures are similar.

Execute DemonstrationPlease follow the procedures below to setup the demonstration: 1. 2. 3. 4. 5. 6. Make sure the DE2-115 is powered off. Mount the ITG adapter onto the 2x20 GPIO 0 expansion header of the DE2-115. Connect the DE2-115 USB-Blaster USB-B port to the PC USB Port with a USB Cable. Power on the DE2-115* FPGA Development Board. Make sure Quartus II 10.1 and NIOS II 10.1 are installed on your system. Copy the folder Demonstrations/SOPC/DE2_115_SOPC_MTL_PAINTER/demo_batch in the MTL System CD onto your system and execute test.bat. 7. Now, you should see the painter GUI on the LCD. *Note: Please attach the 5V USB power adapter when using the DE2 FPGA Development Board.

5.4 Demonstration Source CodeThe source code locations of this demonstration for the various Terasic FPGA boards are shown in Table 5-1. Note: The project is built under Quartus II 10.1, and both Altera VIP license and Terasic Multi-Touch IP license are required for rebuilding the project. Table 5-1 Source Code Locations of Painter DemonstrationFPGA Board Location